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https://github.com/c64scene-ar/llvm-6502.git
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[AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
parent
028e4d27b1
commit
30b2a19f3b
@ -272,6 +272,18 @@ def int_aarch64_neon_vcvtf32_n_u32 :
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def int_aarch64_neon_vcvtf64_n_u64 :
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Intrinsic<[llvm_v1f64_ty], [llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>;
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// Scalar Floating-point Convert To Signed Fixed-point (Immediate)
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def int_aarch64_neon_vcvts_n_s32_f32 :
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Intrinsic<[llvm_v1i32_ty], [llvm_v1f32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_aarch64_neon_vcvtd_n_s64_f64 :
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Intrinsic<[llvm_v1i64_ty], [llvm_v1f64_ty, llvm_i32_ty], [IntrNoMem]>;
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// Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
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def int_aarch64_neon_vcvts_n_u32_f32 :
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Intrinsic<[llvm_v1i32_ty], [llvm_v1f32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_aarch64_neon_vcvtd_n_u64_f64 :
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Intrinsic<[llvm_v1i64_ty], [llvm_v1f64_ty, llvm_i32_ty], [IntrNoMem]>;
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class Neon_SHA_Intrinsic
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: Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v1i32_ty, llvm_v4i32_ty],
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[IntrNoMem]>;
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@ -4058,7 +4058,7 @@ multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
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}
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}
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multiclass NeonI_ScalarShiftImm_scvtf_SD_size<bit u, bits<5> opcode, string asmop> {
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multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
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def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
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bits<5> Imm;
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let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
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@ -4119,6 +4119,16 @@ multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator Sopnode,
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(INSTD FPR64:$Rn, imm:$Imm)>;
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}
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multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator Sopnode,
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SDPatternOperator Dopnode,
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Instruction INSTS,
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Instruction INSTD> {
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def ssi : Pat<(v1i32 (Sopnode (v1f32 FPR32:$Rn), (i32 imm:$Imm))),
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(INSTS FPR32:$Rn, imm:$Imm)>;
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def ddi : Pat<(v1i64 (Dopnode (v1f64 FPR64:$Rn), (i32 imm:$Imm))),
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(INSTD FPR64:$Rn, imm:$Imm)>;
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}
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// Scalar Signed Shift Right (Immediate)
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defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
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defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
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@ -4218,17 +4228,29 @@ defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
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SQRSHRUNsdi>;
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// Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
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defm SCVTF_N : NeonI_ScalarShiftImm_scvtf_SD_size<0b0, 0b11100, "scvtf">;
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defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
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defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_s32,
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int_aarch64_neon_vcvtf64_n_s64,
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SCVTF_Nssi, SCVTF_Nddi>;
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// Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
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defm UCVTF_N : NeonI_ScalarShiftImm_scvtf_SD_size<0b1, 0b11100, "ucvtf">;
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defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
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defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_u32,
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int_aarch64_neon_vcvtf64_n_u64,
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UCVTF_Nssi, UCVTF_Nddi>;
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// Scalar Floating-point Convert To Signed Fixed-point (Immediate)
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defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
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defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_s32_f32,
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int_aarch64_neon_vcvtd_n_s64_f64,
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FCVTZS_Nssi, FCVTZS_Nddi>;
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// Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
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defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
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defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_u32_f32,
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int_aarch64_neon_vcvtd_n_u64_f64,
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FCVTZU_Nssi, FCVTZU_Nddi>;
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// Scalar Integer Add
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let isCommutable = 1 in {
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def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
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@ -5,7 +5,7 @@ define float @test_vcvts_f32_s32(i32 %a) {
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; CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vcvtf.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%vcvtf1.i = tail call <1 x float> @llvm.aarch64.neon.vcvtf32.s32(<1 x i32> %vcvtf.i)
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%vcvtf1.i = call <1 x float> @llvm.aarch64.neon.vcvtf32.s32(<1 x i32> %vcvtf.i)
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%0 = extractelement <1 x float> %vcvtf1.i, i32 0
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ret float %0
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}
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@ -17,7 +17,7 @@ define double @test_vcvtd_f64_s64(i64 %a) {
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; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
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entry:
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%vcvtf.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcvtf1.i = tail call <1 x double> @llvm.aarch64.neon.vcvtf64.s64(<1 x i64> %vcvtf.i)
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%vcvtf1.i = call <1 x double> @llvm.aarch64.neon.vcvtf64.s64(<1 x i64> %vcvtf.i)
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%0 = extractelement <1 x double> %vcvtf1.i, i32 0
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ret double %0
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}
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@ -29,7 +29,7 @@ define float @test_vcvts_f32_u32(i32 %a) {
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; CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vcvtf.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%vcvtf1.i = tail call <1 x float> @llvm.aarch64.neon.vcvtf32.u32(<1 x i32> %vcvtf.i)
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%vcvtf1.i = call <1 x float> @llvm.aarch64.neon.vcvtf32.u32(<1 x i32> %vcvtf.i)
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%0 = extractelement <1 x float> %vcvtf1.i, i32 0
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ret float %0
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}
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@ -41,7 +41,7 @@ define double @test_vcvtd_f64_u64(i64 %a) {
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; CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}
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entry:
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%vcvtf.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcvtf1.i = tail call <1 x double> @llvm.aarch64.neon.vcvtf64.u64(<1 x i64> %vcvtf.i)
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%vcvtf1.i = call <1 x double> @llvm.aarch64.neon.vcvtf64.u64(<1 x i64> %vcvtf.i)
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%0 = extractelement <1 x double> %vcvtf1.i, i32 0
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ret double %0
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}
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@ -53,7 +53,7 @@ define float @test_vcvts_n_f32_s32(i32 %a) {
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; CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}}, #1
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entry:
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%vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0
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%vcvtf1 = tail call <1 x float> @llvm.aarch64.neon.vcvtf32.n.s32(<1 x i32> %vcvtf, i32 1)
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%vcvtf1 = call <1 x float> @llvm.aarch64.neon.vcvtf32.n.s32(<1 x i32> %vcvtf, i32 1)
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%0 = extractelement <1 x float> %vcvtf1, i32 0
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ret float %0
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}
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@ -65,7 +65,7 @@ define double @test_vcvtd_n_f64_s64(i64 %a) {
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; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}, #1
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entry:
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%vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcvtf1 = tail call <1 x double> @llvm.aarch64.neon.vcvtf64.n.s64(<1 x i64> %vcvtf, i32 1)
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%vcvtf1 = call <1 x double> @llvm.aarch64.neon.vcvtf64.n.s64(<1 x i64> %vcvtf, i32 1)
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%0 = extractelement <1 x double> %vcvtf1, i32 0
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ret double %0
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}
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@ -77,7 +77,7 @@ define float @test_vcvts_n_f32_u32(i32 %a) {
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; CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}, #1
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entry:
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%vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0
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%vcvtf1 = tail call <1 x float> @llvm.aarch64.neon.vcvtf32.n.u32(<1 x i32> %vcvtf, i32 1)
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%vcvtf1 = call <1 x float> @llvm.aarch64.neon.vcvtf32.n.u32(<1 x i32> %vcvtf, i32 1)
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%0 = extractelement <1 x float> %vcvtf1, i32 0
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ret float %0
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}
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@ -89,9 +89,57 @@ define double @test_vcvtd_n_f64_u64(i64 %a) {
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; CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}, #1
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entry:
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%vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcvtf1 = tail call <1 x double> @llvm.aarch64.neon.vcvtf64.n.u64(<1 x i64> %vcvtf, i32 1)
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%vcvtf1 = call <1 x double> @llvm.aarch64.neon.vcvtf64.n.u64(<1 x i64> %vcvtf, i32 1)
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%0 = extractelement <1 x double> %vcvtf1, i32 0
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ret double %0
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}
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declare <1 x double> @llvm.aarch64.neon.vcvtf64.n.u64(<1 x i64>, i32)
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define i32 @test_vcvts_n_s32_f32(float %a) {
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; CHECK: test_vcvts_n_s32_f32
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; CHECK: fcvtzs {{s[0-9]+}}, {{s[0-9]+}}, #0
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entry:
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%fcvtzs = insertelement <1 x float> undef, float %a, i32 0
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%fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvts.n.s32.f32(<1 x float> %fcvtzs, i32 0)
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%0 = extractelement <1 x i32> %fcvtzs1, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.vcvts.n.s32.f32(<1 x float>, i32)
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define i64 @test_vcvtd_n_s64_f64(double %a) {
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; CHECK: test_vcvtd_n_s64_f64
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; CHECK: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}, #0
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entry:
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%fcvtzs = insertelement <1 x double> undef, double %a, i32 0
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%fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtd.n.s64.f64(<1 x double> %fcvtzs, i32 0)
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%0 = extractelement <1 x i64> %fcvtzs1, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.vcvtd.n.s64.f64(<1 x double>, i32)
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define i32 @test_vcvts_n_u32_f32(float %a) {
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; CHECK: test_vcvts_n_u32_f32
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; CHECK: fcvtzu {{s[0-9]+}}, {{s[0-9]+}}, #0
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entry:
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%fcvtzu = insertelement <1 x float> undef, float %a, i32 0
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%fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvts.n.u32.f32(<1 x float> %fcvtzu, i32 0)
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%0 = extractelement <1 x i32> %fcvtzu1, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.vcvts.n.u32.f32(<1 x float>, i32)
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define i64 @test_vcvtd_n_u64_f64(double %a) {
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; CHECK: test_vcvtd_n_u64_f64
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; CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}, #0
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entry:
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%fcvtzu = insertelement <1 x double> undef, double %a, i32 0
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%fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtd.n.u64.f64(<1 x double> %fcvtzu, i32 0)
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%0 = extractelement <1 x i64> %fcvtzu1, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.vcvtd.n.u64.f64(<1 x double>, i32)
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@ -5089,6 +5089,42 @@
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// CHECK-ERROR: ucvtf d21, s14, #64
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// CHECK-ERROR: ^
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//----------------------------------------------------------------------
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// Scalar Floating-point Convert To Signed Fixed-point (Immediate)
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//----------------------------------------------------------------------
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fcvtzs s21, s12, #0
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fcvtzs d21, d12, #65
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fcvtzs s21, d12, #1
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// CHECK-ERROR: error: expected integer in range [1, 32]
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// CHECK-ERROR: fcvtzs s21, s12, #0
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: expected integer in range [1, 64]
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// CHECK-ERROR: fcvtzs d21, d12, #65
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: fcvtzs s21, d12, #1
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// CHECK-ERROR: ^
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//----------------------------------------------------------------------
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// Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
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//----------------------------------------------------------------------
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fcvtzu s21, s12, #33
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fcvtzu d21, d12, #0
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fcvtzu s21, d12, #1
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// CHECK-ERROR: error: expected integer in range [1, 32]
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// CHECK-ERROR: fcvtzu s21, s12, #33
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: expected integer in range [1, 64]
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// CHECK-ERROR: fcvtzu d21, d12, #0
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: fcvtzu s21, d12, #1
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// CHECK-ERROR: ^
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//----------------------------------------------------------------------
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// Scalar Unsigned Saturating Extract Narrow
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//----------------------------------------------------------------------
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@ -41,3 +41,23 @@
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// CHECK: ucvtf s22, s13, #32 // encoding: [0xb6,0xe5,0x20,0x7f]
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// CHECK: ucvtf d21, d14, #64 // encoding: [0xd5,0xe5,0x40,0x7f]
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//----------------------------------------------------------------------
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// Scalar Floating-point Convert To Signed Fixed-point (Immediate)
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//----------------------------------------------------------------------
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fcvtzs s21, s12, #1
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fcvtzs d21, d12, #1
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// CHECK: fcvtzs s21, s12, #1 // encoding: [0x95,0xfd,0x3f,0x5f]
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// CHECK: fcvtzs d21, d12, #1 // encoding: [0x95,0xfd,0x7f,0x5f]
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//----------------------------------------------------------------------
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// Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
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//----------------------------------------------------------------------
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fcvtzu s21, s12, #1
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fcvtzu d21, d12, #1
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// CHECK: fcvtzu s21, s12, #1 // encoding: [0x95,0xfd,0x3f,0x7f]
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// CHECK: fcvtzu d21, d12, #1 // encoding: [0x95,0xfd,0x7f,0x7f]
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@ -1972,6 +1972,22 @@ G# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -disassemble < %s |
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0xb6,0xe5,0x20,0x7f
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0xd5,0xe5,0x40,0x7f
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#----------------------------------------------------------------------
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# Scalar Floating-point Convert To Signed Fixed-point (Immediate)
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#----------------------------------------------------------------------
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# CHECK: fcvtzs s21, s12, #1
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# CHECK: fcvtzs d21, d12, #1
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0x95,0xfd,0x3f,0x5f
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0x95,0xfd,0x7f,0x5f
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#----------------------------------------------------------------------
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# Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
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#----------------------------------------------------------------------
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# CHECK: fcvtzu s21, s12, #1
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# CHECK: fcvtzu d21, d12, #1
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0x95,0xfd,0x3f,0x7f
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0x95,0xfd,0x7f,0x7f
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#----------------------------------------------------------------------
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# Vector load/store multiple N-element structure
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#----------------------------------------------------------------------
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