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FNEG/FABS

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21028 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth 2005-04-02 19:04:58 +00:00
parent 4cb11a1de2
commit 30b46d41bc
1 changed files with 17 additions and 4 deletions
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21
lib/Target/Alpha/AlphaISelPattern.cpp
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@ -75,10 +75,6 @@ namespace {
setOperationAction(ISD::MEMSET , MVT::Other, Expand);
setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
// We don't support these yet.
setOperationAction(ISD::FNEG , MVT::f64 , Expand);
setOperationAction(ISD::FABS , MVT::f64 , Expand);
//Doesn't work yet
setOperationAction(ISD::SETCC , MVT::f32, Promote);
@ -541,6 +537,23 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
Node->dump();
assert(0 && "Node not handled!\n");
case ISD::FNEG:
if(ISD::FABS == N.getOperand(0).getOpcode())
{
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
} else {
Tmp1 = SelectExpr(N.getOperand(0));
Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS ;
BuildMI(BB, Opc, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
}
return Result;
case ISD::FABS:
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
return Result;
case ISD::SELECT:
{
//Tmp1 = SelectExpr(N.getOperand(0)); //Cond