mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
CellSPU:
- First patch from Nehal Desai, a new contributor at Aerospace. Nehal's patch fixes sign/zero/any-extending loads for integers and floating point. Example code, compiled w/o debugging or optimization where he first noticed the bug: int main(void) { float a = 99.0; printf("%d\n", a); return 0; } Verified that this code actually works on a Cell SPU. Changes by Scott Michel: - Fix bug in the value type list constructed by SPUISD::LDRESULT to include both the load result's result and chain, not just the chain alone. - Simplify LowerLOAD and remove extraneous and unnecessary chains. - Remove unused SPUISD pseudo instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60526 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -676,7 +676,7 @@ SPUDAGToDAGISel::Select(SDValue Op) {
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Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
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} else {
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Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
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Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Arg, Chain);
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}
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Chain = SDValue(Result, 1);
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@ -436,12 +436,6 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
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node_names[(unsigned) SPUISD::CNTB] = "SPUISD::CNTB";
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node_names[(unsigned) SPUISD::PROMOTE_SCALAR] = "SPUISD::PROMOTE_SCALAR";
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node_names[(unsigned) SPUISD::VEC2PREFSLOT] = "SPUISD::VEC2PREFSLOT";
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node_names[(unsigned) SPUISD::VEC2PREFSLOT_CHAINED]
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= "SPUISD::VEC2PREFSLOT_CHAINED";
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node_names[(unsigned) SPUISD::EXTRACT_I1_ZEXT] = "SPUISD::EXTRACT_I1_ZEXT";
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node_names[(unsigned) SPUISD::EXTRACT_I1_SEXT] = "SPUISD::EXTRACT_I1_SEXT";
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node_names[(unsigned) SPUISD::EXTRACT_I8_ZEXT] = "SPUISD::EXTRACT_I8_ZEXT";
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node_names[(unsigned) SPUISD::EXTRACT_I8_SEXT] = "SPUISD::EXTRACT_I8_SEXT";
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node_names[(unsigned) SPUISD::MPY] = "SPUISD::MPY";
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node_names[(unsigned) SPUISD::MPYU] = "SPUISD::MPYU";
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node_names[(unsigned) SPUISD::MPYH] = "SPUISD::MPYH";
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@ -458,8 +452,6 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
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node_names[(unsigned) SPUISD::ROTQUAD_RZ_BITS] =
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"SPUISD::ROTQUAD_RZ_BITS";
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node_names[(unsigned) SPUISD::ROTBYTES_LEFT] = "SPUISD::ROTBYTES_LEFT";
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node_names[(unsigned) SPUISD::ROTBYTES_LEFT_CHAINED] =
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"SPUISD::ROTBYTES_LEFT_CHAINED";
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node_names[(unsigned) SPUISD::ROTBYTES_LEFT_BITS] =
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"SPUISD::ROTBYTES_LEFT_BITS";
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node_names[(unsigned) SPUISD::SELECT_MASK] = "SPUISD::SELECT_MASK";
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@ -597,13 +589,24 @@ AlignedLoad(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST,
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/*!
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All CellSPU loads and stores are aligned to 16-byte boundaries, so for elements
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within a 16-byte block, we have to rotate to extract the requested element.
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*/
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For extending loads, we also want to ensure that the following sequence is
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emitted, e.g. for MVT::f32 extending load to MVT::f64:
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\verbatim
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%1 v16i8,ch = load
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%2 v16i8,ch = rotate %1
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%3 v4f8, ch = bitconvert %2
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%4 f32 = vec2perfslot %3
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%5 f64 = fp_extend %4
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\endverbatim
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*/
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static SDValue
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LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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LoadSDNode *LN = cast<LoadSDNode>(Op);
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SDValue the_chain = LN->getChain();
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MVT VT = LN->getMemoryVT();
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MVT OpVT = Op.getNode()->getValueType(0);
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MVT InVT = LN->getMemoryVT();
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MVT OutVT = Op.getValueType();
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ISD::LoadExtType ExtType = LN->getExtensionType();
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unsigned alignment = LN->getAlignment();
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SDValue Ops[8];
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@ -613,7 +616,8 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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int offset, rotamt;
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bool was16aligned;
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SDValue result =
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AlignedLoad(Op, DAG, ST, LN,alignment, offset, rotamt, VT, was16aligned);
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AlignedLoad(Op, DAG, ST, LN,alignment, offset, rotamt, InVT,
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was16aligned);
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if (result.getNode() == 0)
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return result;
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@ -625,57 +629,40 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
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if (rotamt != 0 || !was16aligned) {
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SDVTList vecvts = DAG.getVTList(MVT::v16i8, MVT::Other);
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Ops[0] = the_chain;
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Ops[1] = result;
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Ops[0] = result;
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if (was16aligned) {
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Ops[2] = DAG.getConstant(rotamt, MVT::i16);
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Ops[1] = DAG.getConstant(rotamt, MVT::i16);
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} else {
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MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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LoadSDNode *LN1 = cast<LoadSDNode>(result);
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Ops[2] = DAG.getNode(ISD::ADD, PtrVT, LN1->getBasePtr(),
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Ops[1] = DAG.getNode(ISD::ADD, PtrVT, LN1->getBasePtr(),
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DAG.getConstant(rotamt, PtrVT));
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}
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result = DAG.getNode(SPUISD::ROTBYTES_LEFT_CHAINED, vecvts, Ops, 3);
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the_chain = result.getValue(1);
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result = DAG.getNode(SPUISD::ROTBYTES_LEFT, MVT::v16i8, Ops, 2);
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}
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if (VT == OpVT || ExtType == ISD::EXTLOAD) {
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SDVTList scalarvts;
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MVT vecVT = MVT::v16i8;
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// Convert the loaded v16i8 vector to the appropriate vector type
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// specified by the operand:
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MVT vecVT = MVT::getVectorVT(InVT, (128 / InVT.getSizeInBits()));
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result = DAG.getNode(SPUISD::VEC2PREFSLOT, InVT,
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DAG.getNode(ISD::BIT_CONVERT, vecVT, result));
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// Convert the loaded v16i8 vector to the appropriate vector type
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// specified by the operand:
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if (OpVT == VT) {
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if (VT != MVT::i1)
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vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits()));
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} else
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vecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
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// Handle extending loads by extending the scalar result:
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if (ExtType == ISD::SEXTLOAD) {
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result = DAG.getNode(ISD::SIGN_EXTEND, OutVT, result);
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} else if (ExtType == ISD::ZEXTLOAD) {
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result = DAG.getNode(ISD::ZERO_EXTEND, OutVT, result);
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} else if (ExtType == ISD::EXTLOAD) {
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unsigned NewOpc = ISD::ANY_EXTEND;
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Ops[0] = the_chain;
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Ops[1] = DAG.getNode(ISD::BIT_CONVERT, vecVT, result);
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scalarvts = DAG.getVTList((OpVT == VT ? VT : OpVT), MVT::Other);
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result = DAG.getNode(SPUISD::VEC2PREFSLOT_CHAINED, scalarvts, Ops, 2);
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the_chain = result.getValue(1);
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} else {
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// Handle the sign and zero-extending loads for i1 and i8:
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unsigned NewOpC;
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if (OutVT.isFloatingPoint())
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NewOpc = ISD::FP_EXTEND;
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if (ExtType == ISD::SEXTLOAD) {
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NewOpC = (OpVT == MVT::i1
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? SPUISD::EXTRACT_I1_SEXT
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: SPUISD::EXTRACT_I8_SEXT);
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} else {
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assert(ExtType == ISD::ZEXTLOAD);
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NewOpC = (OpVT == MVT::i1
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? SPUISD::EXTRACT_I1_ZEXT
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: SPUISD::EXTRACT_I8_ZEXT);
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}
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result = DAG.getNode(NewOpC, OpVT, result);
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result = DAG.getNode(NewOpc, OutVT, result);
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}
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SDVTList retvts = DAG.getVTList(OpVT, MVT::Other);
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SDVTList retvts = DAG.getVTList(OutVT, MVT::Other);
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SDValue retops[2] = {
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result,
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the_chain
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@ -3034,10 +3021,16 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
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SDValue combinedConst =
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DAG.getConstant(CN0->getZExtValue() + CN1->getZExtValue(), Op0VT);
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DEBUG(cerr << "Replace: (add " << CN0->getZExtValue() << ", "
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<< "(SPUindirect <arg>, " << CN1->getZExtValue() << "))\n");
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DEBUG(cerr << "With: (SPUindirect <arg>, "
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<< CN0->getZExtValue() + CN1->getZExtValue() << ")\n");
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#if defined(NDEBUG)
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if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
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cerr << "\n"
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<< "Replace: (add " << CN0->getZExtValue() << ", "
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<< "(SPUindirect <arg>, " << CN1->getZExtValue() << "))\n"
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<< "With: (SPUindirect <arg>, "
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<< CN0->getZExtValue() + CN1->getZExtValue() << ")\n";
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}
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#endif
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return DAG.getNode(SPUISD::IndirectAddr, Op0VT,
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Op0.getOperand(0), combinedConst);
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}
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@ -3071,11 +3064,14 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
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// (any_extend (SPUextract_elt0 <arg>)) ->
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// (SPUextract_elt0 <arg>)
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// Types must match, however...
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DEBUG(cerr << "Replace: ");
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DEBUG(N->dump(&DAG));
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DEBUG(cerr << "\nWith: ");
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DEBUG(Op0.getNode()->dump(&DAG));
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DEBUG(cerr << "\n");
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#if defined(NDEBUG)
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if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
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cerr << "\nReplace: ";
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N->dump(&DAG);
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cerr << "\nWith: ";
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Op0.getNode()->dump(&DAG);
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cerr << "\n";
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#endif
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return Op0;
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}
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@ -3243,8 +3239,7 @@ SPUTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
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}
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case SPUISD::LDRESULT:
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case SPUISD::VEC2PREFSLOT:
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case SPUISD::VEC2PREFSLOT_CHAINED: {
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case SPUISD::VEC2PREFSLOT: {
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MVT OpVT = Op.getValueType();
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unsigned OpVTBits = OpVT.getSizeInBits();
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uint64_t InMask = OpVT.getIntegerVTBitMask();
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@ -3254,10 +3249,6 @@ SPUTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
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}
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#if 0
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case EXTRACT_I1_ZEXT:
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case EXTRACT_I1_SEXT:
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case EXTRACT_I8_ZEXT:
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case EXTRACT_I8_SEXT:
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case MPY:
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case MPYU:
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case MPYH:
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@ -3272,7 +3263,6 @@ SPUTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
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case SPUISD::ROTQUAD_RZ_BYTES:
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case SPUISD::ROTQUAD_RZ_BITS:
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case SPUISD::ROTBYTES_LEFT:
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case SPUISD::ROTBYTES_LEFT_CHAINED:
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case SPUISD::SELECT_MASK:
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case SPUISD::SELB:
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case SPUISD::FPInterp:
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@ -41,11 +41,6 @@ namespace llvm {
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CNTB, ///< Count leading ones in bytes
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PROMOTE_SCALAR, ///< Promote scalar->vector
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VEC2PREFSLOT, ///< Extract element 0
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VEC2PREFSLOT_CHAINED, ///< Extract element 0, with chain
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EXTRACT_I1_ZEXT, ///< Extract element 0 as i1, zero extend
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EXTRACT_I1_SEXT, ///< Extract element 0 as i1, sign extend
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EXTRACT_I8_ZEXT, ///< Extract element 0 as i8, zero extend
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EXTRACT_I8_SEXT, ///< Extract element 0 as i8, sign extend
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MPY, ///< 16-bit Multiply (low parts of a 32-bit)
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MPYU, ///< Multiply Unsigned
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MPYH, ///< Multiply High
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@ -60,7 +55,6 @@ namespace llvm {
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ROTQUAD_RZ_BYTES, ///< Rotate quad right, by bytes, zero fill
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ROTQUAD_RZ_BITS, ///< Rotate quad right, by bits, zero fill
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ROTBYTES_LEFT, ///< Rotate bytes (loads -> ROTQBYI)
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ROTBYTES_LEFT_CHAINED, ///< Rotate bytes (loads -> ROTQBYI), with chain
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ROTBYTES_LEFT_BITS, ///< Rotate bytes left by bit shift count
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SELECT_MASK, ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
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SELB, ///< Select bits -> (b & mask) | (a & ~mask)
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@ -1288,39 +1288,21 @@ def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)),
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def : Pat<(SPUvec2prefslot (v16i8 VECREG:$rA)),
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(ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
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def : Pat<(SPUvec2prefslot_chained (v16i8 VECREG:$rA)),
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(ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
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def : Pat<(SPUvec2prefslot (v8i16 VECREG:$rA)),
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(ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
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def : Pat<(SPUvec2prefslot_chained (v8i16 VECREG:$rA)),
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(ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
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def : Pat<(SPUvec2prefslot (v4i32 VECREG:$rA)),
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(ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
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def : Pat<(SPUvec2prefslot_chained (v4i32 VECREG:$rA)),
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(ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
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def : Pat<(SPUvec2prefslot (v2i64 VECREG:$rA)),
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(ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
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def : Pat<(SPUvec2prefslot_chained (v2i64 VECREG:$rA)),
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(ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
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def : Pat<(SPUvec2prefslot (v4f32 VECREG:$rA)),
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(ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
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def : Pat<(SPUvec2prefslot_chained (v4f32 VECREG:$rA)),
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(ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
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def : Pat<(SPUvec2prefslot (v2f64 VECREG:$rA)),
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(ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
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def : Pat<(SPUvec2prefslot_chained (v2f64 VECREG:$rA)),
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(ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
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// ORC: Bitwise "or" with complement (c = a | ~b)
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class ORCInst<dag OOL, dag IOL, list<dag> pattern>:
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@ -2147,15 +2129,6 @@ multiclass RotateQuadLeftByBytes
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defm ROTQBY: RotateQuadLeftByBytes;
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def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), R32C:$rB),
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(ROTQBYv16i8 VECREG:$rA, R32C:$rB)>;
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def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), R32C:$rB),
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(ROTQBYv8i16 VECREG:$rA, R32C:$rB)>;
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def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), R32C:$rB),
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(ROTQBYv4i32 VECREG:$rA, R32C:$rB)>;
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def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), R32C:$rB),
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(ROTQBYv2i64 VECREG:$rA, R32C:$rB)>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// Rotate quad by byte (count), immediate
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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@ -2179,15 +2152,6 @@ multiclass RotateQuadByBytesImm
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defm ROTQBYI: RotateQuadByBytesImm;
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def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), (i16 uimm7:$val)),
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(ROTQBYIv16i8 VECREG:$rA, uimm7:$val)>;
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def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), (i16 uimm7:$val)),
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(ROTQBYIv8i16 VECREG:$rA, uimm7:$val)>;
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def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), (i16 uimm7:$val)),
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(ROTQBYIv4i32 VECREG:$rA, uimm7:$val)>;
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def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), (i16 uimm7:$val)),
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(ROTQBYIv2i64 VECREG:$rA, uimm7:$val)>;
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// See ROTQBY note above.
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class ROTQBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
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RI7Form<0b00110011100, OOL, IOL,
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@ -3972,10 +3936,6 @@ def : Pat<(ret),
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// Zero/Any/Sign extensions
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//===----------------------------------------------------------------------===//
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// zext 1->32: Zero extend i1 to i32
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def : Pat<(SPUextract_i1_zext R32C:$rSrc),
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(ANDIr32 R32C:$rSrc, 0x1)>;
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// sext 8->32: Sign extend bytes to words
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def : Pat<(sext_inreg R32C:$rSrc, i8),
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(XSHWr32 (XSBHr32 R32C:$rSrc))>;
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@ -3983,19 +3943,10 @@ def : Pat<(sext_inreg R32C:$rSrc, i8),
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def : Pat<(i32 (sext R8C:$rSrc)),
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(XSHWr16 (XSBHr8 R8C:$rSrc))>;
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def : Pat<(SPUextract_i8_sext VECREG:$rSrc),
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(XSHWr32 (XSBHr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc),
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(v4i32 VECREG:$rSrc))))>;
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// zext 8->16: Zero extend bytes to halfwords
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def : Pat<(i16 (zext R8C:$rSrc)),
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(ANDHIi8i16 R8C:$rSrc, 0xff)>;
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// zext 8->32 from preferred slot in load/store
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def : Pat<(SPUextract_i8_zext VECREG:$rSrc),
|
||||
(ANDIr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc), (v4i32 VECREG:$rSrc)),
|
||||
0xff)>;
|
||||
|
||||
// zext 8->32: Zero extend bytes to words
|
||||
def : Pat<(i32 (zext R8C:$rSrc)),
|
||||
(ANDIi8i32 R8C:$rSrc, 0xff)>;
|
||||
|
@ -125,11 +125,6 @@ def SPUrotquad_rz_bits: SDNode<"SPUISD::ROTQUAD_RZ_BITS",
|
||||
def SPUrotbytes_left: SDNode<"SPUISD::ROTBYTES_LEFT",
|
||||
SPUvecshift_type, []>;
|
||||
|
||||
// Same as above, but the node also has a chain associated (used in loads and
|
||||
// stores)
|
||||
def SPUrotbytes_left_chained : SDNode<"SPUISD::ROTBYTES_LEFT_CHAINED",
|
||||
SPUvecshift_type, [SDNPHasChain]>;
|
||||
|
||||
// Vector rotate left by bytes, but the count is given in bits and the SPU
|
||||
// internally converts it to bytes (saves an instruction to mask off lower
|
||||
// three bits)
|
||||
@ -153,13 +148,6 @@ def SPUpromote_scalar: SDNode<"SPUISD::PROMOTE_SCALAR", SDTpromote_scalar, []>;
|
||||
|
||||
def SPU_vec_demote : SDTypeProfile<1, 1, []>;
|
||||
def SPUvec2prefslot: SDNode<"SPUISD::VEC2PREFSLOT", SPU_vec_demote, []>;
|
||||
def SPU_vec_demote_chained : SDTypeProfile<1, 2, []>;
|
||||
def SPUvec2prefslot_chained: SDNode<"SPUISD::VEC2PREFSLOT_CHAINED",
|
||||
SPU_vec_demote_chained, [SDNPHasChain]>;
|
||||
def SPUextract_i1_sext: SDNode<"SPUISD::EXTRACT_I1_SEXT", SPU_vec_demote, []>;
|
||||
def SPUextract_i1_zext: SDNode<"SPUISD::EXTRACT_I1_ZEXT", SPU_vec_demote, []>;
|
||||
def SPUextract_i8_sext: SDNode<"SPUISD::EXTRACT_I8_SEXT", SPU_vec_demote, []>;
|
||||
def SPUextract_i8_zext: SDNode<"SPUISD::EXTRACT_I8_ZEXT", SPU_vec_demote, []>;
|
||||
|
||||
// Address high and low components, used for [r+r] type addressing
|
||||
def SPUhi : SDNode<"SPUISD::Hi", SDTIntBinOp, []>;
|
||||
|
Loading…
Reference in New Issue
Block a user