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Collapse X86 PSIGNB/PSIGNW/PSIGND node types.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144988 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2011-11-19 07:33:10 +00:00
parent 1666cb6d63
commit 3113384a34
4 changed files with 18 additions and 33 deletions
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21
lib/Target/X86/X86ISelLowering.cpp
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@ -11084,9 +11084,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
case X86ISD::PINSRW: return "X86ISD::PINSRW";
case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
case X86ISD::ANDNP: return "X86ISD::ANDNP";
case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
case X86ISD::PSIGND: return "X86ISD::PSIGND";
case X86ISD::PSIGN: return "X86ISD::PSIGN";
case X86ISD::BLENDV: return "X86ISD::BLENDV";
case X86ISD::FHADD: return "X86ISD::FHADD";
case X86ISD::FHSUB: return "X86ISD::FHSUB";
@ -13928,18 +13926,11 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
Y = Y.getOperand(0);
if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
unsigned Opc = 0;
switch (EltBits) {
case 8: Opc = X86ISD::PSIGNB; break;
case 16: Opc = X86ISD::PSIGNW; break;
case 32: Opc = X86ISD::PSIGND; break;
default: break;
}
if (Opc) {
SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
}
X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() &&
(EltBits == 8 || EltBits == 16 || EltBits == 32)) {
SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X,
Mask.getOperand(1));
return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
}
// PBLENDVB only available on SSE 4.1
if (!(Subtarget->hasSSE41() || Subtarget->hasAVX()))

4
lib/Target/X86/X86ISelLowering.h
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@ -172,8 +172,8 @@ namespace llvm {
/// ANDNP - Bitwise Logical AND NOT of Packed FP values.
ANDNP,
/// PSIGNB/W/D - Copy integer sign.
PSIGNB, PSIGNW, PSIGND,
/// PSIGN - Copy integer sign.
PSIGN,
/// BLEND family of opcodes
BLENDV,

8
lib/Target/X86/X86InstrFragmentsSIMD.td
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@ -51,13 +51,7 @@ def X86pshufb : SDNode<"X86ISD::PSHUFB",
def X86andnp : SDNode<"X86ISD::ANDNP",
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
SDTCisSameAs<0,2>]>>;
def X86psignb : SDNode<"X86ISD::PSIGNB",
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
SDTCisSameAs<0,2>]>>;
def X86psignw : SDNode<"X86ISD::PSIGNW",
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
SDTCisSameAs<0,2>]>>;
def X86psignd : SDNode<"X86ISD::PSIGND",
def X86psign : SDNode<"X86ISD::PSIGN",
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
SDTCisSameAs<0,2>]>>;
def X86pextrb : SDNode<"X86ISD::PEXTRB",

18
lib/Target/X86/X86InstrSSE.td
View File

@ -5363,11 +5363,11 @@ let Predicates = [HasSSSE3] in {
def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
(PSHUFBrm128 VR128:$src, addr:$mask)>;
def : Pat<(v16i8 (X86psignb VR128:$src1, VR128:$src2)),
def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
(PSIGNBrr128 VR128:$src1, VR128:$src2)>;
def : Pat<(v8i16 (X86psignw VR128:$src1, VR128:$src2)),
def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
(PSIGNWrr128 VR128:$src1, VR128:$src2)>;
def : Pat<(v4i32 (X86psignd VR128:$src1, VR128:$src2)),
def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
(PSIGNDrr128 VR128:$src1, VR128:$src2)>;
}
@ -5377,20 +5377,20 @@ let Predicates = [HasAVX] in {
def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
(VPSHUFBrm128 VR128:$src, addr:$mask)>;
def : Pat<(v16i8 (X86psignb VR128:$src1, VR128:$src2)),
def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
(VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
def : Pat<(v8i16 (X86psignw VR128:$src1, VR128:$src2)),
def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
(VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
def : Pat<(v4i32 (X86psignd VR128:$src1, VR128:$src2)),
def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
(VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
}
let Predicates = [HasAVX2] in {
def : Pat<(v32i8 (X86psignb VR256:$src1, VR256:$src2)),
def : Pat<(v32i8 (X86psign VR256:$src1, VR256:$src2)),
(VPSIGNBrr256 VR256:$src1, VR256:$src2)>;
def : Pat<(v16i16 (X86psignw VR256:$src1, VR256:$src2)),
def : Pat<(v16i16 (X86psign VR256:$src1, VR256:$src2)),
(VPSIGNWrr256 VR256:$src1, VR256:$src2)>;
def : Pat<(v8i32 (X86psignd VR256:$src1, VR256:$src2)),
def : Pat<(v8i32 (X86psign VR256:$src1, VR256:$src2)),
(VPSIGNDrr256 VR256:$src1, VR256:$src2)>;
}