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Collapse X86 PSIGNB/PSIGNW/PSIGND node types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144988 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -11084,9 +11084,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::PINSRW: return "X86ISD::PINSRW";
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case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
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case X86ISD::ANDNP: return "X86ISD::ANDNP";
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case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
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case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
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case X86ISD::PSIGND: return "X86ISD::PSIGND";
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case X86ISD::PSIGN: return "X86ISD::PSIGN";
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case X86ISD::BLENDV: return "X86ISD::BLENDV";
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case X86ISD::FHADD: return "X86ISD::FHADD";
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case X86ISD::FHSUB: return "X86ISD::FHSUB";
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@ -13928,19 +13926,12 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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Y = Y.getOperand(0);
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if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
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ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
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X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
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unsigned Opc = 0;
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switch (EltBits) {
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case 8: Opc = X86ISD::PSIGNB; break;
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case 16: Opc = X86ISD::PSIGNW; break;
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case 32: Opc = X86ISD::PSIGND; break;
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default: break;
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}
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if (Opc) {
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SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
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X.getValueType() == MaskVT && X.getValueType() == Y.getValueType() &&
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(EltBits == 8 || EltBits == 16 || EltBits == 32)) {
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SDValue Sign = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X,
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Mask.getOperand(1));
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return DAG.getNode(ISD::BITCAST, DL, VT, Sign);
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}
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}
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// PBLENDVB only available on SSE 4.1
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if (!(Subtarget->hasSSE41() || Subtarget->hasAVX()))
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return SDValue();
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@ -172,8 +172,8 @@ namespace llvm {
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/// ANDNP - Bitwise Logical AND NOT of Packed FP values.
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ANDNP,
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/// PSIGNB/W/D - Copy integer sign.
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PSIGNB, PSIGNW, PSIGND,
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/// PSIGN - Copy integer sign.
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PSIGN,
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/// BLEND family of opcodes
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BLENDV,
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@ -51,13 +51,7 @@ def X86pshufb : SDNode<"X86ISD::PSHUFB",
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def X86andnp : SDNode<"X86ISD::ANDNP",
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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def X86psignb : SDNode<"X86ISD::PSIGNB",
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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def X86psignw : SDNode<"X86ISD::PSIGNW",
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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def X86psignd : SDNode<"X86ISD::PSIGND",
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def X86psign : SDNode<"X86ISD::PSIGN",
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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def X86pextrb : SDNode<"X86ISD::PEXTRB",
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@ -5363,11 +5363,11 @@ let Predicates = [HasSSSE3] in {
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def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
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(PSHUFBrm128 VR128:$src, addr:$mask)>;
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def : Pat<(v16i8 (X86psignb VR128:$src1, VR128:$src2)),
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def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
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(PSIGNBrr128 VR128:$src1, VR128:$src2)>;
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def : Pat<(v8i16 (X86psignw VR128:$src1, VR128:$src2)),
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def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
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(PSIGNWrr128 VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (X86psignd VR128:$src1, VR128:$src2)),
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def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
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(PSIGNDrr128 VR128:$src1, VR128:$src2)>;
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}
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@ -5377,20 +5377,20 @@ let Predicates = [HasAVX] in {
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def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
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(VPSHUFBrm128 VR128:$src, addr:$mask)>;
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def : Pat<(v16i8 (X86psignb VR128:$src1, VR128:$src2)),
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def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
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(VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
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def : Pat<(v8i16 (X86psignw VR128:$src1, VR128:$src2)),
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def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
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(VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
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def : Pat<(v4i32 (X86psignd VR128:$src1, VR128:$src2)),
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def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
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(VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
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}
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let Predicates = [HasAVX2] in {
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def : Pat<(v32i8 (X86psignb VR256:$src1, VR256:$src2)),
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def : Pat<(v32i8 (X86psign VR256:$src1, VR256:$src2)),
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(VPSIGNBrr256 VR256:$src1, VR256:$src2)>;
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def : Pat<(v16i16 (X86psignw VR256:$src1, VR256:$src2)),
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def : Pat<(v16i16 (X86psign VR256:$src1, VR256:$src2)),
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(VPSIGNWrr256 VR256:$src1, VR256:$src2)>;
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def : Pat<(v8i32 (X86psignd VR256:$src1, VR256:$src2)),
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def : Pat<(v8i32 (X86psign VR256:$src1, VR256:$src2)),
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(VPSIGNDrr256 VR256:$src1, VR256:$src2)>;
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}
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