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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-17 06:33:21 +00:00
Convert more calls of getNode() that takes a vector to pass in the start of an array.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29601 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2970,7 +2970,7 @@ SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(Chain);
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Ops.push_back(Value);
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Ops.push_back(StackSlot);
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SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
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SDOperand FIST = DAG.getNode(Opc, MVT::Other, &Ops[0], Ops.size());
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// Load the result.
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return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
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@ -3126,7 +3126,7 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(Op.getOperand(1));
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Ops.push_back(CC);
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Ops.push_back(Cond);
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return DAG.getNode(X86ISD::CMOV, Tys, Ops);
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return DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
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}
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SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
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@ -3154,7 +3154,7 @@ SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
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std::vector<SDOperand> Ops;
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for (unsigned i = 0; i < Cond.getNumOperands(); ++i)
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Ops.push_back(Cond.getOperand(i));
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Cond = DAG.getNode(X86ISD::SETCC, Tys, Ops);
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Cond = DAG.getNode(X86ISD::SETCC, Tys, &Ops[0], Ops.size());
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}
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CC = Cond.getOperand(0);
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@ -3236,7 +3236,7 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
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std::vector<SDOperand> Ops;
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Ops.push_back(Op.getOperand(0));
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Ops.push_back(Op.getOperand(1));
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Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
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Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, &Ops[0], Ops.size());
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} else {
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// FP return with ScalarSSE (return on fp-stack).
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if (DAG.getMachineFunction().liveout_empty())
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@ -3266,14 +3266,14 @@ SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(Chain);
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Ops.push_back(MemLoc);
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Ops.push_back(DAG.getValueType(ArgVT));
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Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
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Copy = DAG.getNode(X86ISD::FLD, Tys, &Ops[0], Ops.size());
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Tys.clear();
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Tys.push_back(MVT::Other);
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Tys.push_back(MVT::Flag);
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Ops.clear();
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Ops.push_back(Copy.getValue(1));
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Ops.push_back(Copy);
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Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
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Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, &Ops[0], Ops.size());
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}
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break;
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}
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@ -3396,7 +3396,7 @@ SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(Chain);
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Ops.push_back(DAG.getValueType(AVT));
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Ops.push_back(InFlag);
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Chain = DAG.getNode(X86ISD::REP_STOS, Tys, Ops);
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Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
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if (TwoRepStos) {
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InFlag = Chain.getValue(1);
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@ -3413,7 +3413,7 @@ SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(Chain);
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Ops.push_back(DAG.getValueType(MVT::i8));
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Ops.push_back(InFlag);
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Chain = DAG.getNode(X86ISD::REP_STOS, Tys, Ops);
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Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
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} else if (BytesLeft) {
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// Issue stores for the last 1 - 3 bytes.
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SDOperand Value;
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@ -3508,7 +3508,7 @@ SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(Chain);
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Ops.push_back(DAG.getValueType(AVT));
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Ops.push_back(InFlag);
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Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, Ops);
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Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
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if (TwoRepMovs) {
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InFlag = Chain.getValue(1);
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@ -3525,7 +3525,7 @@ SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(Chain);
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Ops.push_back(DAG.getValueType(MVT::i8));
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Ops.push_back(InFlag);
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Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, Ops);
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Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
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} else if (BytesLeft) {
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// Issue loads and stores for the last 1 - 3 bytes.
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unsigned Offset = I->getValue() - BytesLeft;
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@ -3571,7 +3571,7 @@ X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
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Tys.push_back(MVT::Flag);
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std::vector<SDOperand> Ops;
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Ops.push_back(Op.getOperand(0));
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SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
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SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &Ops[0], Ops.size());
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Ops.clear();
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Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
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Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
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@ -3579,7 +3579,7 @@ X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(Ops[1].getValue(1));
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Tys[0] = Tys[1] = MVT::i32;
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Tys.push_back(MVT::Other);
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return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
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return DAG.getNode(ISD::MERGE_VALUES, Tys, &Ops[0], Ops.size());
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}
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SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
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@ -4119,12 +4119,13 @@ static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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if (isAlign16)
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return DAG.getLoad(VT, Base->getOperand(0), Base->getOperand(1),
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Base->getOperand(2));
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else
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else {
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// Just use movups, it's shorter.
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return DAG.getNode(ISD::BIT_CONVERT, VT,
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DAG.getNode(X86ISD::LOAD_UA, MVT::v4f32,
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Base->getOperand(0), Base->getOperand(1),
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Base->getOperand(2)));
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}
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}
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SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
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