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X86: Emit Win64 SaveXMM opcodes at the right offset in the right order

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Walk the instructions marked FrameSetup and consider any stores of XMM
registers to the stack as needing a SaveXMM opcode.

This fixes PR22521.

Differential Revision: http://reviews.llvm.org/D7527

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228724 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Majnemer 2015-02-10 19:01:47 +00:00
parent 241ede07b0
commit 3163865f01
2 changed files with 18 additions and 19 deletions
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35
lib/Target/X86/X86FrameLowering.cpp
View File

@ -909,29 +909,29 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
.setMIFlag(MachineInstr::FrameSetup); .setMIFlag(MachineInstr::FrameSetup);
} }
// Skip the rest of register spilling code while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) const MachineInstr *FrameInstr = &*MBBI;
++MBBI; ++MBBI;
if (NeedsWinEH) { if (NeedsWinEH) {
for (const CalleeSavedInfo &Info : MFI->getCalleeSavedInfo()) { int FI;
unsigned Reg = Info.getReg(); if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg)) if (X86::FR64RegClass.contains(Reg)) {
continue; int Offset = getFrameIndexOffset(MF, FI);
assert(X86::FR64RegClass.contains(Reg) && "Unexpected register class"); Offset += SEHFrameOffset;
int Offset = getFrameIndexOffset(MF, Info.getFrameIdx()); BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
Offset += SEHFrameOffset; .addImm(Reg)
.addImm(Offset)
BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM)) .setMIFlag(MachineInstr::FrameSetup);
.addImm(Reg) }
.addImm(Offset) }
.setMIFlag(MachineInstr::FrameSetup);
} }
}
if (NeedsWinEH)
BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue)) BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
.setMIFlag(MachineInstr::FrameSetup); .setMIFlag(MachineInstr::FrameSetup);
}
// Realign stack after we spilled callee-saved registers (so that we'll be // Realign stack after we spilled callee-saved registers (so that we'll be
// able to calculate their offsets from the frame pointer). // able to calculate their offsets from the frame pointer).
@ -1468,8 +1468,7 @@ bool X86FrameLowering::spillCalleeSavedRegisters(
// It can be done by spilling XMMs to stack frame. // It can be done by spilling XMMs to stack frame.
for (unsigned i = CSI.size(); i != 0; --i) { for (unsigned i = CSI.size(); i != 0; --i) {
unsigned Reg = CSI[i-1].getReg(); unsigned Reg = CSI[i-1].getReg();
if (X86::GR64RegClass.contains(Reg) || if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
X86::GR32RegClass.contains(Reg))
continue; continue;
// Add the callee-saved register as live-in. It's killed at the spill. // Add the callee-saved register as live-in. It's killed at the spill.
MBB.addLiveIn(Reg); MBB.addLiveIn(Reg);

2
test/CodeGen/X86/win64_eh.ll
View File

@ -155,9 +155,9 @@ entry:
; WIN64: leaq 128(%rsp), %rbp ; WIN64: leaq 128(%rsp), %rbp
; WIN64: .seh_setframe 5, 128 ; WIN64: .seh_setframe 5, 128
; WIN64: movaps %xmm7, -32(%rbp) # 16-byte Spill ; WIN64: movaps %xmm7, -32(%rbp) # 16-byte Spill
; WIN64: .seh_savexmm 7, 96
; WIN64: movaps %xmm6, -48(%rbp) # 16-byte Spill ; WIN64: movaps %xmm6, -48(%rbp) # 16-byte Spill
; WIN64: .seh_savexmm 6, 80 ; WIN64: .seh_savexmm 6, 80
; WIN64: .seh_savexmm 7, 96
; WIN64: .seh_endprologue ; WIN64: .seh_endprologue
; WIN64: andq $-64, %rsp ; WIN64: andq $-64, %rsp
; WIN64: movaps -48(%rbp), %xmm6 # 16-byte Reload ; WIN64: movaps -48(%rbp), %xmm6 # 16-byte Reload