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Fix for first part of PR2562. Generate the "pinsrw" instruction for inserts

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into v4i16 vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53807 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2008-07-20 02:32:23 +00:00
parent fbbd701bbd
commit 3180e20cda
2 changed files with 17 additions and 0 deletions
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2
lib/Target/X86/X86ISelLowering.cpp
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@ -604,6 +604,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
}
if (Subtarget->hasSSE1()) {

15
test/CodeGen/X86/mmx-pinsrw.ll Normal file
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@ -0,0 +1,15 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx | grep pinsrw | count 1
; PR2562
external global i16 ; <i16*>:0 [#uses=1]
external global <4 x i16> ; <<4 x i16>*>:1 [#uses=2]
declare void @abort()
define void @""() {
load i16* @0 ; <i16>:1 [#uses=1]
load <4 x i16>* @1 ; <<4 x i16>>:2 [#uses=1]
insertelement <4 x i16> %2, i16 %1, i32 0 ; <<4 x i16>>:3 [#uses=1]
store <4 x i16> %3, <4 x i16>* @1
ret void
}