Add a CoveredBySubRegs property to Register descriptions.

When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Hexagon/HexagonRegisterInfo.td

@@ -94,7 +94,7 @@ let Namespace = "Hexagon" in {
   def GP : Ri<31, "r31">, DwarfRegNum<[33]>;
 
   // Aliases of the R* registers used to hold 64-bit int values (doubles).
-  let SubRegIndices = [subreg_loreg, subreg_hireg] in {
+  let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
   def D0  : Rd< 0,  "r1:0", [R0,   R1]>, DwarfRegNum<[32]>;
   def D1  : Rd< 2,  "r3:2", [R2,   R3]>, DwarfRegNum<[34]>;
   def D2  : Rd< 4,  "r5:4", [R4,   R5]>, DwarfRegNum<[36]>;