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[FastISel][AArch64] Cleanup and simplify 'fastSelectInstruction'. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217119 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3550,34 +3550,16 @@ bool AArch64FastISel::SelectBitCast(const Instruction *I) {
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bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
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switch (I->getOpcode()) {
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default:
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return false;
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break;
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case Instruction::Add:
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if (!selectAddSub(I))
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return selectBinaryOp(I, ISD::ADD);
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return true;
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case Instruction::Sub:
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if (!selectAddSub(I))
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return selectBinaryOp(I, ISD::SUB);
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return true;
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case Instruction::FAdd:
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return selectBinaryOp(I, ISD::FADD);
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case Instruction::FSub:
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// FNeg is currently represented in LLVM IR as a special case of FSub.
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if (BinaryOperator::isFNeg(I))
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return selectFNeg(I);
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return selectBinaryOp(I, ISD::FSUB);
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if (selectAddSub(I))
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return true;
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break;
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case Instruction::Mul:
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if (!selectBinaryOp(I, ISD::MUL))
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return SelectMul(I);
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return true;
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case Instruction::FMul:
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return selectBinaryOp(I, ISD::FMUL);
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case Instruction::SDiv:
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return selectBinaryOp(I, ISD::SDIV);
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case Instruction::UDiv:
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return selectBinaryOp(I, ISD::UDIV);
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case Instruction::FDiv:
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return selectBinaryOp(I, ISD::FDIV);
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case Instruction::SRem:
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if (!selectBinaryOp(I, ISD::SREM))
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return SelectRem(I, ISD::SREM);
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@ -3586,51 +3568,22 @@ bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
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if (!selectBinaryOp(I, ISD::UREM))
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return SelectRem(I, ISD::UREM);
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return true;
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case Instruction::FRem:
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return selectBinaryOp(I, ISD::FREM);
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case Instruction::Shl:
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if (!SelectShift(I))
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return selectBinaryOp(I, ISD::SHL);
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return true;
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case Instruction::LShr:
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if (!SelectShift(I))
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return selectBinaryOp(I, ISD::SRL);
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return true;
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case Instruction::AShr:
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if (!SelectShift(I))
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return selectBinaryOp(I, ISD::SRA);
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return true;
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if (SelectShift(I))
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return true;
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break;
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case Instruction::And:
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if (!selectLogicalOp(I))
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return selectBinaryOp(I, ISD::AND);
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return true;
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case Instruction::Or:
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if (!selectLogicalOp(I))
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return selectBinaryOp(I, ISD::OR);
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return true;
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case Instruction::Xor:
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if (!selectLogicalOp(I))
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return selectBinaryOp(I, ISD::XOR);
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return true;
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case Instruction::GetElementPtr:
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return selectGetElementPtr(I);
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if (selectLogicalOp(I))
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return true;
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break;
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case Instruction::Br:
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return SelectBranch(I);
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case Instruction::IndirectBr:
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return SelectIndirectBr(I);
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case Instruction::Unreachable:
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if (TM.Options.TrapUnreachable)
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return fastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
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else
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return true;
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case Instruction::Alloca:
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// FunctionLowering has the static-sized case covered.
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if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
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return true;
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// Dynamic-sized alloca is not handled yet.
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return false;
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case Instruction::Call:
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return selectCall(I);
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case Instruction::BitCast:
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if (!FastISel::selectBitCast(I))
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return SelectBitCast(I);
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@ -3663,24 +3616,6 @@ bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
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return true;
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case Instruction::UIToFP:
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return SelectIntToFP(I, /*Signed=*/false);
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case Instruction::IntToPtr: // Deliberate fall-through.
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case Instruction::PtrToInt: {
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EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
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EVT DstVT = TLI.getValueType(I->getType());
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if (DstVT.bitsGT(SrcVT))
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return selectCast(I, ISD::ZERO_EXTEND);
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if (DstVT.bitsLT(SrcVT))
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return selectCast(I, ISD::TRUNCATE);
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unsigned Reg = getRegForValue(I->getOperand(0));
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if (!Reg)
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return false;
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updateValueMap(I, Reg);
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return true;
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}
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case Instruction::ExtractValue:
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return selectExtractValue(I);
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case Instruction::PHI:
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llvm_unreachable("FastISel shouldn't visit PHI nodes!");
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case Instruction::Load:
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return SelectLoad(I);
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case Instruction::Store:
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@ -3694,6 +3629,8 @@ bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
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return SelectRet(I);
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}
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// fall-back to target-independent instruction selection.
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return selectOperator(I, I->getOpcode());
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// Silence warnings.
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(void)&CC_AArch64_DarwinPCS_VarArg;
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}
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