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Remove uses of the TargetMachine from FunctionLoweringInfo
via caching TargetLowering and using the MachineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219375 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -51,10 +51,10 @@ class Value;
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/// function that is used when lowering a region of the function.
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/// function that is used when lowering a region of the function.
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///
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///
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class FunctionLoweringInfo {
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class FunctionLoweringInfo {
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const TargetMachine &TM;
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public:
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public:
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const Function *Fn;
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const Function *Fn;
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MachineFunction *MF;
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MachineFunction *MF;
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const TargetLowering *TLI;
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MachineRegisterInfo *RegInfo;
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MachineRegisterInfo *RegInfo;
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BranchProbabilityInfo *BPI;
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BranchProbabilityInfo *BPI;
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/// CanLowerReturn - true iff the function's return value can be lowered to
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/// CanLowerReturn - true iff the function's return value can be lowered to
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@ -127,8 +127,6 @@ public:
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/// SelectionDAGISel::PrepareEHLandingPad().
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/// SelectionDAGISel::PrepareEHLandingPad().
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unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
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unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
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explicit FunctionLoweringInfo(const TargetMachine &TM) : TM(TM) {}
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/// set - Initialize this FunctionLoweringInfo with the given Function
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/// set - Initialize this FunctionLoweringInfo with the given Function
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/// and its associated MachineFunction.
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/// and its associated MachineFunction.
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///
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///
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@ -80,18 +80,16 @@ static ISD::NodeType getPreferredExtendForValue(const Value *V) {
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void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
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void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
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SelectionDAG *DAG) {
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SelectionDAG *DAG) {
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const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
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Fn = &fn;
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Fn = &fn;
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MF = &mf;
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MF = &mf;
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TLI = MF->getSubtarget().getTargetLowering();
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RegInfo = &MF->getRegInfo();
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RegInfo = &MF->getRegInfo();
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// Check whether the function can return without sret-demotion.
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// Check whether the function can return without sret-demotion.
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SmallVector<ISD::OutputArg, 4> Outs;
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SmallVector<ISD::OutputArg, 4> Outs;
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GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
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GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
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CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
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CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
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Fn->isVarArg(),
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Fn->isVarArg(), Outs, Fn->getContext());
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Outs, Fn->getContext());
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// Initialize the mapping of values to registers. This is only set up for
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// Initialize the mapping of values to registers. This is only set up for
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// instruction values that are used outside of the block that defines
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// instruction values that are used outside of the block that defines
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@ -107,8 +105,8 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
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Type *Ty = AI->getAllocatedType();
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Type *Ty = AI->getAllocatedType();
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uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
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uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
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unsigned Align =
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unsigned Align =
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std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
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std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
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AI->getAlignment());
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AI->getAlignment());
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TySize *= CUI->getZExtValue(); // Get total allocated size.
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TySize *= CUI->getZExtValue(); // Get total allocated size.
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if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
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if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
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@ -122,7 +120,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
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AI->getAllocatedType()),
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AI->getAllocatedType()),
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AI->getAlignment());
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AI->getAlignment());
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unsigned StackAlign =
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unsigned StackAlign =
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TM.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
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MF->getSubtarget().getFrameLowering()->getStackAlignment();
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if (Align <= StackAlign)
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if (Align <= StackAlign)
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Align = 0;
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Align = 0;
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// Inform the Frame Information that we have variable-sized objects.
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// Inform the Frame Information that we have variable-sized objects.
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@ -142,9 +140,9 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
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if (Op.Type == InlineAsm::isClobber) {
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if (Op.Type == InlineAsm::isClobber) {
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// Clobbers don't have SDValue operands, hence SDValue().
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// Clobbers don't have SDValue operands, hence SDValue().
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TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
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TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
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std::pair<unsigned, const TargetRegisterClass*> PhysReg =
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std::pair<unsigned, const TargetRegisterClass *> PhysReg =
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TLI->getRegForInlineAsmConstraint(Op.ConstraintCode,
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TLI->getRegForInlineAsmConstraint(Op.ConstraintCode,
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Op.ConstraintVT);
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Op.ConstraintVT);
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if (PhysReg.first == SP)
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if (PhysReg.first == SP)
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MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true);
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MF->getFrameInfo()->setHasInlineAsmWithSPAdjust(true);
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}
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}
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@ -281,7 +279,7 @@ void FunctionLoweringInfo::clear() {
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/// CreateReg - Allocate a single virtual register for the given type.
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/// CreateReg - Allocate a single virtual register for the given type.
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unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
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unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
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return RegInfo->createVirtualRegister(
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return RegInfo->createVirtualRegister(
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TM.getSubtargetImpl()->getTargetLowering()->getRegClassFor(VT));
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MF->getSubtarget().getTargetLowering()->getRegClassFor(VT));
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}
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}
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/// CreateRegs - Allocate the appropriate number of virtual registers of
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/// CreateRegs - Allocate the appropriate number of virtual registers of
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@ -292,7 +290,7 @@ unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
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/// will assign registers for each member or element.
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/// will assign registers for each member or element.
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///
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///
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unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
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unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
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const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
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const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
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SmallVector<EVT, 4> ValueVTs;
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(*TLI, Ty, ValueVTs);
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ComputeValueVTs(*TLI, Ty, ValueVTs);
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@ -341,8 +339,6 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
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if (!Ty->isIntegerTy() || Ty->isVectorTy())
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if (!Ty->isIntegerTy() || Ty->isVectorTy())
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return;
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return;
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const TargetLowering *TLI = TM.getSubtargetImpl()->getTargetLowering();
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SmallVector<EVT, 1> ValueVTs;
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SmallVector<EVT, 1> ValueVTs;
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ComputeValueVTs(*TLI, Ty, ValueVTs);
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ComputeValueVTs(*TLI, Ty, ValueVTs);
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assert(ValueVTs.size() == 1 &&
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assert(ValueVTs.size() == 1 &&
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@ -336,7 +336,7 @@ void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
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SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
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SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
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CodeGenOpt::Level OL) :
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CodeGenOpt::Level OL) :
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MachineFunctionPass(ID), TM(tm),
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MachineFunctionPass(ID), TM(tm),
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FuncInfo(new FunctionLoweringInfo(TM)),
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FuncInfo(new FunctionLoweringInfo()),
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CurDAG(new SelectionDAG(tm, OL)),
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CurDAG(new SelectionDAG(tm, OL)),
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SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
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SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
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GFI(),
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GFI(),
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