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Who thought up this crazy formatting scheme?

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40905 91177308-0d34-0410-b5e6-96231b3b80d8
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Reid Spencer 2007-08-07 17:57:36 +00:00
parent d5d9e6f0c9
commit 31cac2e04a
1 changed files with 23 additions and 83 deletions
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docs/CommandGuide/lli.pod
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@ -121,29 +121,17 @@ equivalent hardware instructions.
=head1 CODE GENERATION OPTIONS =head1 CODE GENERATION OPTIONS
=over 4 =over
=item B<-code-model>=I<model> =item B<-code-model>=I<model>
Choose the code model from: Choose the code model from:
=back default: Target default code model
small: Small code model
=over 8 kernel: Kernel code model
medium: Medium code model
=item I<default>: Target default code model large: Large code model
=item I<small>: Small code model
=item I<kernel>: Kernel code model
=item I<medium>: Medium code model
=item I<large>: Large code model
=back
=over 4
=item B<-disable-post-RA-scheduler> =item B<-disable-post-RA-scheduler>
@ -172,91 +160,43 @@ Don't place zero-initialized symbols into the BSS section.
Instruction schedulers available (before register allocation): Instruction schedulers available (before register allocation):
=back =default: Best scheduler for the target
=none: No scheduling: breadth first sequencing
=over 8 =simple: Simple two pass scheduling: minimize critical path and maximize processor utilization
=simple-noitin: Simple two pass scheduling: Same as simple except using generic latency
=item I<=default>: Best scheduler for the target =list-burr: Bottom-up register reduction list scheduling
=list-tdrr: Top-down register reduction list scheduling
=item I<=none>: No scheduling: breadth first sequencing =list-td: Top-down list scheduler -print-machineinstrs - Print generated machine code
=item I<=simple>: Simple two pass scheduling: minimize critical path and maximize processor utilization
=item I<=simple-noitin>: Simple two pass scheduling: Same as simple except using generic latency
=item I<=list-burr>: Bottom-up register reduction list scheduling
=item I<=list-tdrr>: Top-down register reduction list scheduling
=item I<=list-td>: Top-down list scheduler -print-machineinstrs - Print generated machine code
=back
=over 4
=item B<-regalloc>=I<allocator> =item B<-regalloc>=I<allocator>
Register allocator to use: (default = linearscan) Register allocator to use: (default = linearscan)
=back =bigblock: Big-block register allocator
=linearscan: linear scan register allocator =local - local register allocator
=over 8 =simple: simple register allocator
=item I<=bigblock>: Big-block register allocator
=item I<=linearscan>: linear scan register allocator =local - local register allocator
=item I<=simple>: simple register allocator
=back
=over 4
=item B<-relocation-model>=I<model> =item B<-relocation-model>=I<model>
Choose relocation model from: Choose relocation model from:
=back =default: Target default relocation model
=static: Non-relocatable code =pic - Fully relocatable, position independent code
=over 8 =dynamic-no-pic: Relocatable external references, non-relocatable code
=item I<=default>: Target default relocation model
=item I<=static>: Non-relocatable code =pic - Fully relocatable, position independent code
=item I<=dynamic-no-pic>: Relocatable external references, non-relocatable code
=back
=over 4
=item B<-spiller> =item B<-spiller>
Spiller to use: (default: local) Spiller to use: (default: local)
=back =simple: simple spiller
=local: local spiller
=over 8
=item I<=simple>: simple spiller
=item I<=local>: local spiller
=back
=over 4
=item B<-x86-asm-syntax>=I<syntax> =item B<-x86-asm-syntax>=I<syntax>
Choose style of code to emit from X86 backend: Choose style of code to emit from X86 backend:
=back =att: Emit AT&T-style assembly
=intel: Emit Intel-style assembly
=over 8
=item I<=att>: Emit AT&T-style assembly
=item I<=intel>: Emit Intel-style assembly
=back =back