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Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-09-23 21:07:25 +00:00
parent df0caeb6ec
commit 31d485ec9a
2 changed files with 3 additions and 3 deletions
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2
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -2660,7 +2660,7 @@ static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
break; break;
default: { default: {
unsigned Rt = fieldFromInstruction32(Insn, 12, 4); unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
} }

4
test/MC/Disassembler/ARM/thumb2.txt
View File

@ -649,14 +649,14 @@
# CHECK: ldrh.w r5, [r6, #33] # CHECK: ldrh.w r5, [r6, #33]
# CHECK: ldrh.w r5, [r6, #257] # CHECK: ldrh.w r5, [r6, #257]
# CHECK: ldrh.w lr, [r7, #257] # CHECK: ldrh.w lr, [r7, #257]
# CHECK: ldrh.w sp, [pc, #-21] # CHECK: ldrh.w r0, [pc, #-21]
0x35 0xf8 0x04 0x5c 0x35 0xf8 0x04 0x5c
0x35 0x8c 0x35 0x8c
0xb6 0xf8 0x21 0x50 0xb6 0xf8 0x21 0x50
0xb6 0xf8 0x01 0x51 0xb6 0xf8 0x01 0x51
0xb7 0xf8 0x01 0xe1 0xb7 0xf8 0x01 0xe1
0x3f 0xf8 0x15 0xd0 0x3f 0xf8 0x15 0x00
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------