From 31d938a6b1173c642f975d78417459d4d8cd3677 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Mon, 14 May 2012 15:12:37 +0000 Subject: [PATCH] Record the ad hoc aliasing graph in CodeGenRegister. The ad hoc aliasing specified in the 'Aliases' list in .td files is currently only used by computeOverlaps(). It will soon be needed to build accurate register units as well, so build the undirected graph in CodeGenRegister::buildObjectGraph() instead. Aliasing is a symmetric relationship with only one direction specified in the .td files. Make sure both directions are represented in getExplicitAliases(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156762 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/CodeGenRegisters.cpp | 16 +++++++++++----- utils/TableGen/CodeGenRegisters.h | 10 ++++++++++ 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/utils/TableGen/CodeGenRegisters.cpp b/utils/TableGen/CodeGenRegisters.cpp index 499292a1969..797c31a9345 100644 --- a/utils/TableGen/CodeGenRegisters.cpp +++ b/utils/TableGen/CodeGenRegisters.cpp @@ -108,6 +108,15 @@ void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { // This is used by computeSecondarySubRegs() to find candidates. if (CoveredBySubRegs && !ExplicitSubRegs.empty()) ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this); + + // Add ad hoc alias links. This is a symmetric relationship betwen two + // registers, so build a symmetric graph by adding links in both ends. + std::vector Aliases = TheDef->getValueAsListOfDefs("Aliases"); + for (unsigned i = 0, e = Aliases.size(); i != e; ++i) { + CodeGenRegister *Reg = RegBank.getReg(Aliases[i]); + ExplicitAliases.push_back(Reg); + Reg->ExplicitAliases.push_back(this); + } } const std::string &CodeGenRegister::getName() const { @@ -1529,16 +1538,13 @@ computeOverlaps(std::map &Map) { Overlaps.insert(Supers.begin(), Supers.end()); // Form symmetrical relations from the special Aliases[] lists. - std::vector RegList = Reg->TheDef->getValueAsListOfDefs("Aliases"); + ArrayRef RegList = Reg->getExplicitAliases(); for (unsigned i2 = 0, e2 = RegList.size(); i2 != e2; ++i2) { - CodeGenRegister *Reg2 = getReg(RegList[i2]); - CodeGenRegister::Set &Overlaps2 = Map[Reg2]; + CodeGenRegister *Reg2 = RegList[i2]; const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs(); // Reg overlaps Reg2 which implies it overlaps supers(Reg2). Overlaps.insert(Reg2); Overlaps.insert(Supers2.begin(), Supers2.end()); - Overlaps2.insert(Reg); - Overlaps2.insert(Supers.begin(), Supers.end()); } } diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index 7e2c07ee580..491a91667a0 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -142,6 +142,13 @@ namespace llvm { return SuperRegs; } + // Get the list of ad hoc aliases. The graph is symmetric, so the list + // contains all registers in 'Aliases', and all registers that mention this + // register in 'Aliases'. + ArrayRef getExplicitAliases() const { + return ExplicitAliases; + } + // Get the topological signature of this register. This is a small integer // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have // identical sub-register structure. That is, they support the same set of @@ -191,6 +198,9 @@ namespace llvm { SmallVector ExplicitSubRegIndices; SmallVector ExplicitSubRegs; + // Explicit ad hoc aliases, symmetrized to form an undirected graph. + SmallVector ExplicitAliases; + // Super-registers where this is the first explicit sub-register. SuperRegList LeadingSuperRegs;