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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-08 08:54:58 +00:00
Turn few asserts into errors / unreachable's
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76313 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -183,7 +183,7 @@ void SystemZAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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if (printInstruction(MI))
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return;
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assert(0 && "Should not happen");
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llvm_unreachable("Unreachable!");
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}
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void SystemZAsmPrinter::printPCRelImmOperand(const MachineInstr *MI, int OpNum) {
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@ -282,7 +282,7 @@ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
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switch (MO.getTargetFlags()) {
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default:
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assert(0 && "Unknown target flag on GV operand");
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llvm_unreachable("Unknown target flag on GV operand");
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case SystemZII::MO_NO_FLAG:
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break;
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case SystemZII::MO_GOTENT: O << "@GOTENT"; break;
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@ -161,7 +161,7 @@ SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
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default:
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assert(0 && "unimplemented operand");
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llvm_unreachable("Should not custom lower this!");
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return SDValue();
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}
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}
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@ -177,7 +177,7 @@ SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
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unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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switch (CC) {
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default:
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assert(0 && "Unsupported calling convention");
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llvm_unreachable("Unsupported calling convention");
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case CallingConv::C:
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case CallingConv::Fast:
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return LowerCCCArguments(Op, DAG);
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@ -189,7 +189,7 @@ SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
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unsigned CallingConv = TheCall->getCallingConv();
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switch (CallingConv) {
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default:
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assert(0 && "Unsupported calling convention");
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llvm_unreachable("Unsupported calling convention");
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case CallingConv::Fast:
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case CallingConv::C:
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return LowerCCCCallTo(Op, DAG, CallingConv);
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@ -215,7 +215,8 @@ SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
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CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
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assert(!isVarArg && "Varargs not supported yet");
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if (isVarArg)
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llvm_report_error("Varargs not supported yet");
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SmallVector<SDValue, 16> ArgValues;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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@ -534,7 +535,8 @@ SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
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bool isUnsigned = false;
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SystemZCC::CondCodes TCC;
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switch (CC) {
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default: assert(0 && "Invalid integer condition!");
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default:
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llvm_unreachable("Invalid integer condition!");
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case ISD::SETEQ:
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case ISD::SETOEQ:
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TCC = SystemZCC::E;
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@ -81,7 +81,7 @@ void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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} else if (RC == &SystemZ::GR128RegClass) {
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Opc = SystemZ::MOV128mr;
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} else
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assert(0 && "Unsupported regclass to store");
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llvm_unreachable("Unsupported regclass to store");
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addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
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.addReg(SrcReg, getKillRegState(isKill));
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@ -110,7 +110,7 @@ void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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} else if (RC == &SystemZ::GR128RegClass) {
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Opc = SystemZ::MOV128rm;
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} else
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assert(0 && "Unsupported regclass to load");
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llvm_unreachable("Unsupported regclass to load");
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addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
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}
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@ -584,7 +584,7 @@ const TargetInstrDesc&
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SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
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switch (CC) {
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default:
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assert(0 && "Unknown condition code!");
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llvm_unreachable("Unknown condition code!");
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case SystemZCC::O: return get(SystemZ::JO);
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case SystemZCC::H: return get(SystemZ::JH);
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case SystemZCC::NLE: return get(SystemZ::JNLE);
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@ -627,7 +627,7 @@ SystemZCC::CondCodes
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SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const {
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switch (CC) {
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default:
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assert(0 && "Invalid condition!");
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llvm_unreachable("Invalid condition!");
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case SystemZCC::O: return SystemZCC::NO;
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case SystemZCC::H: return SystemZCC::NH;
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case SystemZCC::NLE: return SystemZCC::LE;
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@ -649,7 +649,7 @@ const TargetInstrDesc&
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SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
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switch (Opc) {
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default:
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assert(0 && "Don't have long disp version of this instruction");
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llvm_unreachable("Don't have long disp version of this instruction");
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case SystemZ::MOV32mr: return get(SystemZ::MOV32mry);
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case SystemZ::MOV32rm: return get(SystemZ::MOV32rmy);
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case SystemZ::MOVSX32rm16: return get(SystemZ::MOVSX32rm16y);
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