mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 23:29:22 +00:00
Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.
The instructions can be selected directly from the intrinsics. We will need to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but those are not yet implemented. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80117 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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62c77d33b1
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@ -1263,117 +1263,6 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
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}
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case ARMISD::VLD2D: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc = 0;
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EVT VT = Op.getValueType();
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled VLD2D type");
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case MVT::v8i8: Opc = ARM::VLD2d8; break;
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case MVT::v4i16: Opc = ARM::VLD2d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD2d32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
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}
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case ARMISD::VLD3D: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc = 0;
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EVT VT = Op.getValueType();
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled VLD3D type");
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case MVT::v8i8: Opc = ARM::VLD3d8; break;
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case MVT::v4i16: Opc = ARM::VLD3d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD3d32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4);
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}
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case ARMISD::VLD4D: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc = 0;
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EVT VT = Op.getValueType();
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled VLD4D type");
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case MVT::v8i8: Opc = ARM::VLD4d8; break;
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case MVT::v4i16: Opc = ARM::VLD4d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD4d32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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std::vector<EVT> ResTys(4, VT);
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ResTys.push_back(MVT::Other);
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return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 4);
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}
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case ARMISD::VST2D: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc = 0;
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switch (N->getOperand(2).getValueType().getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled VST2D type");
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case MVT::v8i8: Opc = ARM::VST2d8; break;
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case MVT::v4i16: Opc = ARM::VST2d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST2d32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(2), N->getOperand(3), Chain };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
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}
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case ARMISD::VST3D: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc = 0;
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switch (N->getOperand(2).getValueType().getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled VST3D type");
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case MVT::v8i8: Opc = ARM::VST3d8; break;
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case MVT::v4i16: Opc = ARM::VST3d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST3d32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(2), N->getOperand(3),
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N->getOperand(4), Chain };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
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}
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case ARMISD::VST4D: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc))
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return NULL;
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unsigned Opc = 0;
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switch (N->getOperand(2).getValueType().getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled VST4D type");
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case MVT::v8i8: Opc = ARM::VST4d8; break;
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case MVT::v4i16: Opc = ARM::VST4d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST4d32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(2), N->getOperand(3),
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N->getOperand(4), N->getOperand(5), Chain };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
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}
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case ARMISD::VZIP: {
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unsigned Opc = 0;
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EVT VT = N->getValueType(0);
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@ -1425,6 +1314,121 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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return CurDAG->getTargetNode(Opc, dl, VT, VT,
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N->getOperand(0), N->getOperand(1));
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}
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case ISD::INTRINSIC_VOID:
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case ISD::INTRINSIC_W_CHAIN: {
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unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
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EVT VT = N->getValueType(0);
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unsigned Opc = 0;
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switch (IntNo) {
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default:
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break;
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case Intrinsic::arm_neon_vld2: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld2 type");
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case MVT::v8i8: Opc = ARM::VLD2d8; break;
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case MVT::v4i16: Opc = ARM::VLD2d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD2d32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
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}
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case Intrinsic::arm_neon_vld3: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld3 type");
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case MVT::v8i8: Opc = ARM::VLD3d8; break;
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case MVT::v4i16: Opc = ARM::VLD3d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD3d32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4);
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}
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case Intrinsic::arm_neon_vld4: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld4 type");
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case MVT::v8i8: Opc = ARM::VLD4d8; break;
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case MVT::v4i16: Opc = ARM::VLD4d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VLD4d32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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std::vector<EVT> ResTys(4, VT);
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ResTys.push_back(MVT::Other);
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return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 4);
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}
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case Intrinsic::arm_neon_vst2: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst2 type");
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case MVT::v8i8: Opc = ARM::VST2d8; break;
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case MVT::v4i16: Opc = ARM::VST2d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST2d32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(3), N->getOperand(4), Chain };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
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}
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case Intrinsic::arm_neon_vst3: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst3 type");
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case MVT::v8i8: Opc = ARM::VST3d8; break;
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case MVT::v4i16: Opc = ARM::VST3d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST3d32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(3), N->getOperand(4),
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N->getOperand(5), Chain };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
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}
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case Intrinsic::arm_neon_vst4: {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vst4 type");
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case MVT::v8i8: Opc = ARM::VST4d8; break;
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case MVT::v4i16: Opc = ARM::VST4d16; break;
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case MVT::v2f32:
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case MVT::v2i32: Opc = ARM::VST4d32; break;
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}
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SDValue Chain = N->getOperand(0);
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
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N->getOperand(3), N->getOperand(4),
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N->getOperand(5), N->getOperand(6), Chain };
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return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
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}
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}
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}
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}
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return SelectCode(Op);
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@ -483,12 +483,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
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case ARMISD::VDUP: return "ARMISD::VDUP";
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case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
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case ARMISD::VLD2D: return "ARMISD::VLD2D";
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case ARMISD::VLD3D: return "ARMISD::VLD3D";
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case ARMISD::VLD4D: return "ARMISD::VLD4D";
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case ARMISD::VST2D: return "ARMISD::VST2D";
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case ARMISD::VST3D: return "ARMISD::VST3D";
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case ARMISD::VST4D: return "ARMISD::VST4D";
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case ARMISD::VEXT: return "ARMISD::VEXT";
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case ARMISD::VREV64: return "ARMISD::VREV64";
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case ARMISD::VREV32: return "ARMISD::VREV32";
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@ -1345,52 +1339,45 @@ SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
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}
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static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
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unsigned Opcode) {
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unsigned NumVecs) {
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SDNode *Node = Op.getNode();
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EVT VT = Node->getValueType(0);
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DebugLoc dl = Op.getDebugLoc();
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if (!VT.is64BitVector())
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return SDValue(); // unimplemented
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// No expansion needed for 64-bit vectors.
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if (VT.is64BitVector())
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return SDValue();
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SDValue Ops[] = { Node->getOperand(0),
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Node->getOperand(2) };
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return DAG.getNode(Opcode, dl, Node->getVTList(), Ops, 2);
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// FIXME: We need to expand VLD3 and VLD4 of 128-bit vectors into separate
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// operations to load the even and odd registers.
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return SDValue();
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}
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static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG,
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unsigned Opcode, unsigned NumVecs) {
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unsigned NumVecs) {
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SDNode *Node = Op.getNode();
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EVT VT = Node->getOperand(3).getValueType();
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DebugLoc dl = Op.getDebugLoc();
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if (!VT.is64BitVector())
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return SDValue(); // unimplemented
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// No expansion needed for 64-bit vectors.
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if (VT.is64BitVector())
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return SDValue();
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SmallVector<SDValue, 6> Ops;
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Ops.push_back(Node->getOperand(0));
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Ops.push_back(Node->getOperand(2));
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for (unsigned N = 0; N < NumVecs; ++N)
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Ops.push_back(Node->getOperand(N + 3));
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return DAG.getNode(Opcode, dl, MVT::Other, Ops.data(), Ops.size());
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// FIXME: We need to expand VST3 and VST4 of 128-bit vectors into separate
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// operations to store the even and odd registers.
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return SDValue();
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}
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SDValue
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ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
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unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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switch (IntNo) {
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case Intrinsic::arm_neon_vld2:
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return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD2D);
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case Intrinsic::arm_neon_vld3:
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return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD3D);
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return LowerNeonVLDIntrinsic(Op, DAG, 3);
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case Intrinsic::arm_neon_vld4:
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return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD4D);
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case Intrinsic::arm_neon_vst2:
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return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST2D, 2);
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return LowerNeonVLDIntrinsic(Op, DAG, 4);
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case Intrinsic::arm_neon_vst3:
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return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST3D, 3);
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return LowerNeonVSTIntrinsic(Op, DAG, 3);
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case Intrinsic::arm_neon_vst4:
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return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST4D, 4);
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return LowerNeonVSTIntrinsic(Op, DAG, 4);
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default: return SDValue(); // Don't custom lower most intrinsics.
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}
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}
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@ -119,14 +119,6 @@ namespace llvm {
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VDUP,
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VDUPLANE,
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// Vector load/store with (de)interleaving
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VLD2D,
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VLD3D,
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VLD4D,
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VST2D,
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VST3D,
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VST4D,
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// Vector shuffles:
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VEXT, // extract
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VREV64, // reverse elements within 64-bit doublewords
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