6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-10-20 09:24:58 +00:00
Code Issues Projects Releases Wiki Activity

Add a predicate

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27129 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-25 22:56:35 +00:00
parent 6ea2dee6f6
commit 322dcd379e
1 changed files with 7 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -453,6 +453,13 @@ namespace ISD {
BUILTIN_OP_END
};
/// Node predicates
/// isBuildVectorAllOnesInteger - Return true if the specified node is a
/// BUILD_VECTOR where all of the elements are ~0 or undef.
bool isBuildVectorAllOnesInteger(const SDNode *N);
//===--------------------------------------------------------------------===//
/// ISD::CondCode enum - These are ordered carefully to make the bitfields
/// below work out, when considering SETFALSE (something that never exists