From 325f0a129e57ff5d1842edd0b4b7473a4d6b47f6 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 11 Aug 2006 16:47:32 +0000 Subject: [PATCH] Fix miscompilation of float vector returns. Compile code to this: _func: vsldoi v2, v3, v2, 12 vsldoi v2, v2, v2, 4 blr instead of: _func: vsldoi v2, v3, v2, 12 vsldoi v2, v2, v2, 4 *** vor f1, v2, v2 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29607 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCISelLowering.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 1cb69d1e006..73610fc4826 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1238,11 +1238,11 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { ArgReg = PPC::R3; } else if (ArgVT == MVT::i64) { ArgReg = PPC::X3; - } else if (MVT::isFloatingPoint(ArgVT)) { - ArgReg = PPC::F1; - } else { - assert(MVT::isVector(ArgVT)); + } else if (MVT::isVector(ArgVT)) { ArgReg = PPC::V2; + } else { + assert(MVT::isFloatingPoint(ArgVT)); + ArgReg = PPC::F1; } Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),