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[AArch64][FastISel] Variant of the logical instructions that use two input

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registers cannot write on SP.

rdar://problem/20748715


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236352 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet 2015-05-01 21:34:57 +00:00
parent 204bccaa24
commit 32675bbfd0
2 changed files with 20 additions and 1 deletions
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2
lib/Target/AArch64/AArch64FastISel.cpp
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@ -2573,7 +2573,7 @@ bool AArch64FastISel::optimizeSelect(const SelectInst *SI) {
Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1);
Src1IsKill = true;
}
unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32spRegClass, Src1Reg,
unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,
Src1IsKill, Src2Reg, Src2IsKill);
updateValueMap(SI, ResultReg);
return true;

19
test/CodeGen/AArch64/arm64-fast-isel.ll
View File

@ -114,3 +114,22 @@ entry:
}
declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)
define void @logicalReg() {
; Make sure we generate a logical reg = reg, reg instruction without any
; machine verifier errors.
; CHECK-LABEL: logicalReg:
; CHECK: orr w{{[0-9]+}}, w{{[0-9]+}}, w{{[0-9]+}}
; CHECK: ret
entry:
br i1 undef, label %cond.end, label %cond.false
cond.false:
%cond = select i1 undef, i1 true, i1 false
br label %cond.end
cond.end:
%cond13 = phi i1 [ %cond, %cond.false ], [ true, %entry ]
ret void
}