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Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
da7f5f1c1d
commit
326efe5891
@ -1785,8 +1785,6 @@ def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
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BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
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def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
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// TODO: SXT(A){B|H}16
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// Zero extenders
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let AddedComplexity = 16 in {
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@ -3931,3 +3929,17 @@ def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
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(t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
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def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
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(t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
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def : t2InstAlias<"sxtb${p} $Rd, $Rm",
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(t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
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def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
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(t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
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def : t2InstAlias<"sxth${p} $Rd, $Rm",
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(t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
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// Extend instruction w/o the ".w" optional width specifier.
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def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
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(t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
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def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
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(t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
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def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
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(t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
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@ -2254,15 +2254,11 @@ ARMAsmParser::OperandMatchResultTy ARMAsmParser::
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parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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const AsmToken &Tok = Parser.getTok();
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SMLoc S = Tok.getLoc();
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if (Tok.isNot(AsmToken::Identifier)) {
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Error(S, "rotate operator 'ror' expected");
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return MatchOperand_ParseFail;
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}
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if (Tok.isNot(AsmToken::Identifier))
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return MatchOperand_NoMatch;
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StringRef ShiftName = Tok.getString();
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if (ShiftName != "ror" && ShiftName != "ROR") {
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Error(S, "rotate operator 'ror' expected");
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return MatchOperand_ParseFail;
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}
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if (ShiftName != "ror" && ShiftName != "ROR")
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return MatchOperand_NoMatch;
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Parser.Lex(); // Eat the operator.
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// A '#' and a rotate amount.
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@ -3867,6 +3863,28 @@ processInstruction(MCInst &Inst,
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}
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break;
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}
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case ARM::t2SXTH:
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case ARM::t2SXTB: {
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// If we can use the 16-bit encoding and the user didn't explicitly
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// request the 32-bit variant, transform it here.
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if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
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isARMLowRegister(Inst.getOperand(1).getReg()) &&
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Inst.getOperand(2).getImm() == 0 &&
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(!static_cast<ARMOperand*>(Operands[2])->isToken() ||
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static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
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unsigned NewOpc = (Inst.getOpcode() == ARM::t2SXTH) ?
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ARM::tSXTH : ARM::tSXTB;
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// The operands aren't the same for thumb1 (no rotate operand).
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MCInst TmpInst;
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TmpInst.setOpcode(NewOpc);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(Inst.getOperand(3));
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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}
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break;
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}
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case ARM::t2IT: {
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// The mask bits for all but the first condition are represented as
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// the low bit of the condition code value implies 't'. We currently
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@ -2504,3 +2504,111 @@ _func:
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@ CHECK: ite hi @ encoding: [0x8c,0xbf]
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@ CHECK: sxtahhi r6, r1, r6 @ encoding: [0x01,0xfa,0x86,0xf6]
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@ CHECK: sxtahls r2, r2, r4, ror #16 @ encoding: [0x02,0xfa,0xa4,0xf2]
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@------------------------------------------------------------------------------
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@ SXTB
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@------------------------------------------------------------------------------
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sxtb r5, r6, ror #0
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sxtb r6, r9, ror #8
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sxtb r8, r3, ror #24
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ite ge
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sxtbge r2, r4
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sxtblt r5, r1, ror #16
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@ CHECK: sxtb r5, r6 @ encoding: [0x75,0xb2]
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@ CHECK: sxtb.w r6, r9, ror #8 @ encoding: [0x4f,0xfa,0x99,0xf6]
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@ CHECK: sxtb.w r8, r3, ror #24 @ encoding: [0x4f,0xfa,0xb3,0xf8]
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@ CHECK: ite ge @ encoding: [0xac,0xbf]
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@ CHECK: sxtbge r2, r4 @ encoding: [0x62,0xb2]
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@ CHECK: sxtblt.w r5, r1, ror #16 @ encoding: [0x4f,0xfa,0xa1,0xf5]
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@------------------------------------------------------------------------------
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@ SXTB16
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@------------------------------------------------------------------------------
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sxtb16 r1, r4
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sxtb16 r6, r7, ror #0
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sxtb16 r3, r1, ror #16
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ite cs
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sxtb16cs r3, r5, ror #8
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sxtb16lo r2, r3, ror #24
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@ CHECK: sxtb16 r1, r4 @ encoding: [0x2f,0xfa,0x84,0xf1]
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@ CHECK: sxtb16 r6, r7 @ encoding: [0x2f,0xfa,0x87,0xf6]
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@ CHECK: sxtb16 r3, r1, ror #16 @ encoding: [0x2f,0xfa,0xa1,0xf3]
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@ CHECK: ite hs @ encoding: [0x2c,0xbf]
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@ CHECK: sxtb16hs r3, r5, ror #8 @ encoding: [0x2f,0xfa,0x95,0xf3]
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@ CHECK: sxtb16lo r2, r3, ror #24 @ encoding: [0x2f,0xfa,0xb3,0xf2]
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@------------------------------------------------------------------------------
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@ SXTH
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@------------------------------------------------------------------------------
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sxth r1, r6, ror #0
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sxth r3, r8, ror #8
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sxth r9, r3, ror #24
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itt ne
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sxthne r3, r9
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sxthne r2, r2, ror #16
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@ CHECK: sxth r1, r6 @ encoding: [0x31,0xb2]
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@ CHECK: sxth.w r3, r8, ror #8 @ encoding: [0x0f,0xfa,0x98,0xf3]
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@ CHECK: sxth.w r9, r3, ror #24 @ encoding: [0x0f,0xfa,0xb3,0xf9]
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@ CHECK: itt ne @ encoding: [0x1c,0xbf]
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@ CHECK: sxthne.w r3, r9 @ encoding: [0x0f,0xfa,0x89,0xf3]
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@ CHECK: sxthne.w r2, r2, ror #16 @ encoding: [0x0f,0xfa,0xa2,0xf2]
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@------------------------------------------------------------------------------
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@ SXTB
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@------------------------------------------------------------------------------
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sxtb r5, r6, ror #0
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sxtb.w r6, r9, ror #8
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sxtb r8, r3, ror #24
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ite ge
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sxtbge r2, r4
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sxtblt r5, r1, ror #16
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@ CHECK: sxtb r5, r6 @ encoding: [0x75,0xb2]
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@ CHECK: sxtb.w r6, r9, ror #8 @ encoding: [0x4f,0xfa,0x99,0xf6]
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@ CHECK: sxtb.w r8, r3, ror #24 @ encoding: [0x4f,0xfa,0xb3,0xf8]
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@ CHECK: ite ge @ encoding: [0xac,0xbf]
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@ CHECK: sxtbge r2, r4 @ encoding: [0x62,0xb2]
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@ CHECK: sxtblt.w r5, r1, ror #16 @ encoding: [0x4f,0xfa,0xa1,0xf5]
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@------------------------------------------------------------------------------
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@ SXTB16
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@------------------------------------------------------------------------------
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sxtb16 r1, r4
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sxtb16 r6, r7, ror #0
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sxtb16 r3, r1, ror #16
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ite cs
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sxtb16cs r3, r5, ror #8
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sxtb16lo r2, r3, ror #24
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@ CHECK: sxtb16 r1, r4 @ encoding: [0x2f,0xfa,0x84,0xf1]
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@ CHECK: sxtb16 r6, r7 @ encoding: [0x2f,0xfa,0x87,0xf6]
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@ CHECK: sxtb16 r3, r1, ror #16 @ encoding: [0x2f,0xfa,0xa1,0xf3]
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@ CHECK: ite hs @ encoding: [0x2c,0xbf]
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@ CHECK: sxtb16hs r3, r5, ror #8 @ encoding: [0x2f,0xfa,0x95,0xf3]
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@ CHECK: sxtb16lo r2, r3, ror #24 @ encoding: [0x2f,0xfa,0xb3,0xf2]
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@------------------------------------------------------------------------------
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@ SXTH
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@------------------------------------------------------------------------------
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sxth r1, r6, ror #0
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sxth.w r3, r8, ror #8
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sxth r9, r3, ror #24
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itt ne
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sxthne r3, r9
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sxthne r2, r2, ror #16
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@ CHECK: sxth r1, r6 @ encoding: [0x31,0xb2]
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@ CHECK: sxth.w r3, r8, ror #8 @ encoding: [0x0f,0xfa,0x98,0xf3]
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@ CHECK: sxth.w r9, r3, ror #24 @ encoding: [0x0f,0xfa,0xb3,0xf9]
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@ CHECK: itt ne @ encoding: [0x1c,0xbf]
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@ CHECK: sxthne.w r3, r9 @ encoding: [0x0f,0xfa,0x89,0xf3]
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@ CHECK: sxthne.w r2, r2, ror #16 @ encoding: [0x0f,0xfa,0xa2,0xf2]
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@ -248,7 +248,7 @@
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sxtah r9, r3, r3, ror #-8
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sxtb16ge r2, r3, lsr #24
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@ CHECK-ERRORS: error: rotate operator 'ror' expected
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: sxtb r8, r3, #8
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: '#' expected
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@ -269,7 +269,7 @@
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@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24
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@ CHECK-ERRORS: sxtah r9, r3, r3, ror #-8
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: rotate operator 'ror' expected
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: sxtb16ge r2, r3, lsr #24
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@ CHECK-ERRORS: ^
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