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Make minor adjustments to whitespace and comments to reduce differences
between SSE1 instructions and their respective SSE2 analogues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37718 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -392,7 +392,6 @@ def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
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// Alias bitwise logical operations using SSE logical ops on packed FP values.
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let isTwoAddress = 1 in {
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let isCommutable = 1 in {
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def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
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"andps {$src2, $dst|$dst, $src2}",
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@ -418,9 +417,11 @@ def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
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[(set FR32:$dst, (X86fxor FR32:$src1,
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(X86loadpf32 addr:$src2)))]>;
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def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
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def FsANDNPSrr : PSI<0x55, MRMSrcReg,
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(ops FR32:$dst, FR32:$src1, FR32:$src2),
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"andnps {$src2, $dst|$dst, $src2}", []>;
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def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
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def FsANDNPSrm : PSI<0x55, MRMSrcMem,
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(ops FR32:$dst, FR32:$src1, f128mem:$src2),
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"andnps {$src2, $dst|$dst, $src2}", []>;
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}
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@ -440,8 +441,8 @@ multiclass scalar_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
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bit Commutable = 0> {
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// Scalar operation, reg+reg.
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def SSrr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
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!strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
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[(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
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!strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
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[(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
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let isCommutable = Commutable;
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}
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@ -498,20 +499,22 @@ def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
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[(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
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let isTwoAddress = 1 in {
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let AddedComplexity = 20 in {
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def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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"movlps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
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MOVLP_shuffle_mask)))]>;
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def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
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"movhps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
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MOVHP_shuffle_mask)))]>;
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} // AddedComplexity
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let AddedComplexity = 20 in {
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def MOVLPSrm : PSI<0x12, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f64mem:$src2),
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"movlps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
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MOVLP_shuffle_mask)))]>;
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def MOVHPSrm : PSI<0x16, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f64mem:$src2),
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"movhps {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst,
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(v4f32 (vector_shuffle VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
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MOVHP_shuffle_mask)))]>;
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} // AddedComplexity
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} // isTwoAddress
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def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
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@ -955,7 +958,7 @@ def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
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"comisd {$src2, $src1|$src1, $src2}",
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[(X86comi (v2f64 VR128:$src1), (load addr:$src2))]>;
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// Aliases of packed instructions for scalar use. These all have names that
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// Aliases of packed SSE2 instructions for scalar use. These all have names that
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// start with 'Fs'.
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// Alias instructions that map fld0 to pxor for sse.
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@ -963,16 +966,16 @@ def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
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"pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
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Requires<[HasSSE2]>, TB, OpSize;
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// Alias instructions to do FR64 reg-to-reg copy using movapd. Upper bits are
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// Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
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// disregarded.
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def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
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"movapd {$src, $dst|$dst, $src}", []>;
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"movapd {$src, $dst|$dst, $src}", []>;
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// Alias instructions to load FR64 from f128mem using movapd. Upper bits are
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// Alias instruction to load FR64 from f128mem using movapd. Upper bits are
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// disregarded.
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def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
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"movapd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (X86loadpf64 addr:$src))]>;
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"movapd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (X86loadpf64 addr:$src))]>;
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// Alias bitwise logical operations using SSE logical ops on packed FP values.
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let isTwoAddress = 1 in {
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