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[mips] Fix more incorrect uses of HasMips64 and isMips64()

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Summary:
- Conditional moves acting on 64-bit GPR's should require MIPS-IV rather than MIPS64
- ISD::MUL, and ISD::MULH[US] should be lowered on all 64-bit ISA's

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

I've added additional testcases to cover as much of the codegen changes
affecting MIPS-IV as I can. Where I've been unable to find an existing
MIPS64 testcase that can be re-used for MIPS-IV (mainly tests covering
ISD::GlobalAddress and similar), I at least agree that MIPS-IV should
behave like MIPS64. Further testcases that are fixed by this patch will follow
in my next commit. The testcases from that commit that fail for MIPS-IV without
this patch are:
    LLVM :: CodeGen/Mips/2010-07-20-Switch.ll
    LLVM :: CodeGen/Mips/cmov.ll
    LLVM :: CodeGen/Mips/eh-dwarf-cfa.ll
    LLVM :: CodeGen/Mips/largeimmprinting.ll
    LLVM :: CodeGen/Mips/longbranch.ll
    LLVM :: CodeGen/Mips/mips64-f128.ll
    LLVM :: CodeGen/Mips/mips64directive.ll
    LLVM :: CodeGen/Mips/mips64ext.ll
    LLVM :: CodeGen/Mips/mips64fpldst.ll
    LLVM :: CodeGen/Mips/mips64intldst.ll
    LLVM :: CodeGen/Mips/mips64load-store-left-right.ll
    LLVM :: CodeGen/Mips/sint-fp-store_pattern.ll

Reviewers: dsanders

Reviewed By: dsanders

CC: matheusalmeida

Differential Revision: http://reviews.llvm.org/D3343

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206183 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2014-04-14 15:44:42 +00:00
parent 555f97f2bc
commit 327be6483d
7 changed files with 35 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/Mips/MipsCondMov.td
View File

@ -139,7 +139,7 @@ def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,
let isCodeGenOnly = 1 in
def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]>;
CMov_I_F_FM<19, 16>, Requires<[IsGP64bit, HasStdEnc]>;
let Predicates = [NotFP64bit, HasStdEnc] in {
def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
@ -166,14 +166,14 @@ def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
let isCodeGenOnly = 1 in
def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>,
CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]>;
CMov_F_I_FM<1>, Requires<[IsGP64bit, HasStdEnc]>;
def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
CMov_F_I_FM<0>;
let isCodeGenOnly = 1 in
def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]>;
CMov_F_I_FM<0>, Requires<[IsGP64bit, HasStdEnc]>;
def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
CMov_F_F_FM<16, 1>;
@ -198,7 +198,7 @@ let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>;
defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>;
let Predicates = [HasMips64, HasStdEnc] in {
let Predicates = [IsGP64bit, HasStdEnc] in {
defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64,
SLTiu64>;
@ -213,7 +213,7 @@ let Predicates = [HasMips64, HasStdEnc] in {
}
defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>;
let Predicates = [HasMips64, HasStdEnc] in {
let Predicates = [IsGP64bit, HasStdEnc] in {
defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>;
defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>;
defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>;
@ -222,7 +222,7 @@ let Predicates = [HasMips64, HasStdEnc] in {
defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>;
defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>;
let Predicates = [HasMips64, HasStdEnc] in {
let Predicates = [IsGP64bit, HasStdEnc] in {
defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
SLTiu64>;
defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>;

10
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -245,7 +245,7 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
if (hasMips64()) {
if (isGP64bit()) {
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
@ -257,14 +257,14 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
}
if (!hasMips64()) {
if (!isGP64bit()) {
setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
}
setOperationAction(ISD::ADD, MVT::i32, Custom);
if (hasMips64())
if (isGP64bit())
setOperationAction(ISD::ADD, MVT::i64, Custom);
setOperationAction(ISD::SDIV, MVT::i32, Expand);
@ -361,7 +361,7 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
setOperationAction(ISD::BSWAP, MVT::i64, Expand);
}
if (hasMips64()) {
if (isGP64bit()) {
setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
@ -377,7 +377,7 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM)
setTargetDAGCombine(ISD::OR);
setTargetDAGCombine(ISD::ADD);
setMinFunctionAlignment(hasMips64() ? 3 : 2);
setMinFunctionAlignment(isGP64bit() ? 3 : 2);
setStackPointerRegisterToSaveRestore(isN64() ? Mips::SP_64 : Mips::SP);

4
lib/Target/Mips/MipsInstrInfo.td
View File

@ -160,6 +160,10 @@ def HasMips32 : Predicate<"Subtarget.hasMips32()">,
AssemblerPredicate<"FeatureMips32">;
def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
AssemblerPredicate<"FeatureMips32r2">;
def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
AssemblerPredicate<"FeatureGP64Bit">;
def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
AssemblerPredicate<"!FeatureGP64Bit">;
def HasMips64 : Predicate<"Subtarget.hasMips64()">,
AssemblerPredicate<"FeatureMips64">;
def IsGP32 : Predicate<"!Subtarget.isGP64()">,

4
lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -119,10 +119,10 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
if (Subtarget->hasCnMips())
setOperationAction(ISD::MUL, MVT::i64, Legal);
else if (hasMips64())
else if (isGP64bit())
setOperationAction(ISD::MUL, MVT::i64, Custom);
if (hasMips64()) {
if (isGP64bit()) {
setOperationAction(ISD::MULHS, MVT::i64, Custom);
setOperationAction(ISD::MULHU, MVT::i64, Custom);
}

3
test/CodeGen/Mips/cmov.ll
View File

@ -1,6 +1,7 @@
; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=O32
; RUN: llc -march=mips -regalloc=basic < %s | FileCheck %s -check-prefix=O32
; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck %s -check-prefix=N64
; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 < %s | FileCheck %s -check-prefix=N64
@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
@i3 = common global i32* null, align 4
@ -238,4 +239,4 @@ define i32 @slti6(i32 %a) nounwind readnone {
; O32-DAG: xori [[R1]], [[R1]], 1
; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], 3
; O32-NOT: movn
; O32:.size slti6
; O32:.size slti6

18
test/CodeGen/Mips/mips64instrs.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS4 %s
; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS64 %s
@gll0 = common global i64 0, align 8
@gll1 = common global i64 0, align 8
@ -135,14 +136,24 @@ declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
define i64 @f18(i64 %X) nounwind readnone {
entry:
; CHECK: dclz $2, $4
; CHECK-LABEL: f18:
; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
; MIPS4-NOT: dclz
; MIPS64: dclz $2, $4
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
ret i64 %tmp1
}
define i64 @f19(i64 %X) nounwind readnone {
entry:
; CHECK: dclo $2, $4
; CHECK-LABEL: f19:
; The MIPS4 version is too long to reasonably test. At least check we don't get dclo
; MIPS4-NOT: dclo
; MIPS64: dclo $2, $4
%neg = xor i64 %X, -1
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
ret i64 %tmp1
@ -150,6 +161,7 @@ entry:
define i64 @f20(i64 %a, i64 %b) nounwind readnone {
entry:
; CHECK-LABEL: f20:
; CHECK: nor
%or = or i64 %b, %a
%neg = xor i64 %or, -1

1
test/CodeGen/Mips/mips64muldiv.ll
View File

@ -1,3 +1,4 @@
; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
define i64 @m0(i64 %a0, i64 %a1) nounwind readnone {