mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
2 more vdup.32 cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78419 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
fcc716352b
commit
32a1b25781
@ -1769,6 +1769,20 @@ def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
|
||||
def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
|
||||
def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
|
||||
|
||||
def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
|
||||
(outs DPR:$dst), (ins SPR:$src),
|
||||
"vdup.32\t$dst, ${src:lane}", "",
|
||||
[(set DPR:$dst, (v2f32 (splat_lo
|
||||
(scalar_to_vector SPR:$src),
|
||||
undef)))]>;
|
||||
|
||||
def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
|
||||
(outs QPR:$dst), (ins SPR:$src),
|
||||
"vdup.32\t$dst, ${src:lane}", "",
|
||||
[(set QPR:$dst, (v4f32 (splat_lo
|
||||
(scalar_to_vector SPR:$src),
|
||||
undef)))]>;
|
||||
|
||||
// VMOVN : Vector Narrowing Move
|
||||
defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
|
||||
int_arm_neon_vmovn>;
|
||||
|
@ -345,6 +345,11 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
|
||||
O << '{'
|
||||
<< TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
|
||||
<< '}';
|
||||
} else if (Modifier && strcmp(Modifier, "lane") == 0) {
|
||||
unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
|
||||
unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 0 : 1,
|
||||
&ARM::DPRRegClass);
|
||||
O << TRI->getAsmName(DReg) << '[' << (RegNum & 1) << ']';
|
||||
} else {
|
||||
O << TRI->getAsmName(Reg);
|
||||
}
|
||||
|
@ -1,7 +1,7 @@
|
||||
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
|
||||
; RUN: grep vdup.8 %t | count 4
|
||||
; RUN: grep vdup.16 %t | count 4
|
||||
; RUN: grep vdup.32 %t | count 8
|
||||
; RUN: grep vdup.32 %t | count 10
|
||||
|
||||
define <8 x i8> @v_dup8(i8 %A) nounwind {
|
||||
%tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
|
||||
@ -132,3 +132,17 @@ define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
|
||||
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
|
||||
ret <4 x float> %tmp2
|
||||
}
|
||||
|
||||
define <2 x float> @v_shuffledupfloat2(float* %A) nounwind {
|
||||
%tmp0 = load float* %A
|
||||
%tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
|
||||
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
|
||||
ret <2 x float> %tmp2
|
||||
}
|
||||
|
||||
define <4 x float> @v_shuffledupQfloat2(float* %A) nounwind {
|
||||
%tmp0 = load float* %A
|
||||
%tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
|
||||
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
|
||||
ret <4 x float> %tmp2
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user