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Replace a couple if/elses around similar calls with conditional operators on the varying arguments. No functional change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164886 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-09-29 06:54:22 +00:00
parent 72f7b0811e
commit 32b7343a96
1 changed files with 6 additions and 17 deletions
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23
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -3221,11 +3221,8 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
if ((LShVal + RShVal) != OpSizeInBits)
return 0;
SDValue Rot;
if (HasROTL)
Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
else
Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
// If there is an AND of either shifted operand, apply it to the result.
if (LHSMask.getNode() || RHSMask.getNode()) {
@ -3258,12 +3255,8 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
if (ConstantSDNode *SUBC =
dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
if (SUBC->getAPIntValue() == OpSizeInBits) {
if (HasROTL)
return DAG.getNode(ISD::ROTL, DL, VT,
LHSShiftArg, LHSShiftAmt).getNode();
else
return DAG.getNode(ISD::ROTR, DL, VT,
LHSShiftArg, RHSShiftAmt).getNode();
return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg,
HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
}
}
}
@ -3275,12 +3268,8 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
if (ConstantSDNode *SUBC =
dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
if (SUBC->getAPIntValue() == OpSizeInBits) {
if (HasROTR)
return DAG.getNode(ISD::ROTR, DL, VT,
LHSShiftArg, RHSShiftAmt).getNode();
else
return DAG.getNode(ISD::ROTL, DL, VT,
LHSShiftArg, LHSShiftAmt).getNode();
return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg,
HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
}
}
}