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Fix for PR2472. Use movss to set lower 32-bits of a zero XMM vector.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53386 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-07-10 01:08:23 +00:00
parent ae55e04d7a
commit 331e2bd942
2 changed files with 12 additions and 0 deletions
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2
lib/Target/X86/X86InstrSSE.td
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@ -2870,6 +2870,8 @@ def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
(MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
(MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
(MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
}
// Splat v2f64 / v2i64

10
test/CodeGen/X86/vec_set-J.ll Normal file
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@ -0,0 +1,10 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movss
; PR2472
define <4 x i32> @a(<4 x i32> %a) nounwind {
entry:
%vecext = extractelement <4 x i32> %a, i32 0
insertelement <4 x i32> zeroinitializer, i32 %vecext, i32 0
%add = add <4 x i32> %a, %0
ret <4 x i32> %add
}