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Encode the conditional execution predicate when JITing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57258 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -256,8 +256,8 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
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unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary) {
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// FIXME: Assume CC is AL for now.
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Binary |= ARMCC::AL << 28;
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << 28;
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switch (TID.TSFlags & ARMII::FormMask) {
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default:
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@ -376,8 +376,8 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
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unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary) {
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// FIXME: Assume CC is AL for now.
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Binary |= ARMCC::AL << 28;
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << 28;
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// Encode S bit if MI modifies CPSR.
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Binary |= getAddrMode1SBit(MI, TID);
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@ -429,8 +429,8 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
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unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary) {
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// FIXME: Assume CC is AL for now.
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Binary |= ARMCC::AL << 28;
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << 28;
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// Set first operand
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
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@ -470,8 +470,8 @@ unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
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unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary) {
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// FIXME: Assume CC is AL for now.
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Binary |= ARMCC::AL << 28;
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << 28;
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// Set first operand
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
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@ -507,8 +507,8 @@ unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
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unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary) {
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// FIXME: Assume CC is AL for now.
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Binary |= ARMCC::AL << 28;
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << 28;
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// Set first operand
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
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@ -217,6 +217,12 @@ public:
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// Predication support.
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virtual bool isPredicated(const MachineInstr *MI) const;
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ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
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int PIdx = MI->findFirstPredOperandIdx();
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return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
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: ARMCC::AL;
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}
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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