6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-17 05:29:24 +00:00
Code Issues Projects Releases Wiki Activity

Encode the conditional execution predicate when JITing.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57258 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2008-10-07 19:05:35 +00:00
parent 2cb48eaeb8
commit 3341262de2
2 changed files with 16 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -256,8 +256,8 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned Binary) {
// FIXME: Assume CC is AL for now.
Binary |= ARMCC::AL << 28;
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << 28;
switch (TID.TSFlags & ARMII::FormMask) {
default:
@ -376,8 +376,8 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned Binary) {
// FIXME: Assume CC is AL for now.
Binary |= ARMCC::AL << 28;
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << 28;
// Encode S bit if MI modifies CPSR.
Binary |= getAddrMode1SBit(MI, TID);
@ -429,8 +429,8 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned Binary) {
// FIXME: Assume CC is AL for now.
Binary |= ARMCC::AL << 28;
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << 28;
// Set first operand
Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
@ -470,8 +470,8 @@ unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned Binary) {
// FIXME: Assume CC is AL for now.
Binary |= ARMCC::AL << 28;
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << 28;
// Set first operand
Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
@ -507,8 +507,8 @@ unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
const TargetInstrDesc &TID,
unsigned Binary) {
// FIXME: Assume CC is AL for now.
Binary |= ARMCC::AL << 28;
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << 28;
// Set first operand
Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;

6
lib/Target/ARM/ARMInstrInfo.h
View File

@ -217,6 +217,12 @@ public:
// Predication support.
virtual bool isPredicated(const MachineInstr *MI) const;
ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
int PIdx = MI->findFirstPredOperandIdx();
return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
: ARMCC::AL;
}
virtual
bool PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const;