mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-05-23 11:38:38 +00:00
Remove the -color-ss-with-regs option.
It was off by default. The new register allocators don't have the problems that made it necessary to reallocate registers during stack slot coloring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144481 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
6e49be7101
commit
334575e79b
@ -40,18 +40,9 @@ DisableSharing("no-stack-slot-sharing",
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cl::init(false), cl::Hidden,
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cl::init(false), cl::Hidden,
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cl::desc("Suppress slot sharing during stack coloring"));
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cl::desc("Suppress slot sharing during stack coloring"));
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static cl::opt<bool>
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ColorWithRegsOpt("color-ss-with-regs",
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cl::init(false), cl::Hidden,
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cl::desc("Color stack slots with free registers"));
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static cl::opt<int> DCELimit("ssc-dce-limit", cl::init(-1), cl::Hidden);
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static cl::opt<int> DCELimit("ssc-dce-limit", cl::init(-1), cl::Hidden);
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STATISTIC(NumEliminated, "Number of stack slots eliminated due to coloring");
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STATISTIC(NumEliminated, "Number of stack slots eliminated due to coloring");
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STATISTIC(NumRegRepl, "Number of stack slot refs replaced with reg refs");
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STATISTIC(NumLoadElim, "Number of loads eliminated");
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STATISTIC(NumStoreElim, "Number of stores eliminated");
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STATISTIC(NumDead, "Number of trivially dead stack accesses eliminated");
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STATISTIC(NumDead, "Number of trivially dead stack accesses eliminated");
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namespace {
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namespace {
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@ -127,22 +118,8 @@ namespace {
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bool OverlapWithAssignments(LiveInterval *li, int Color) const;
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bool OverlapWithAssignments(LiveInterval *li, int Color) const;
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int ColorSlot(LiveInterval *li);
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int ColorSlot(LiveInterval *li);
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bool ColorSlots(MachineFunction &MF);
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bool ColorSlots(MachineFunction &MF);
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bool ColorSlotsWithFreeRegs(SmallVector<int, 16> &SlotMapping,
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SmallVector<SmallVector<int, 4>, 16> &RevMap,
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BitVector &SlotIsReg);
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void RewriteInstruction(MachineInstr *MI, int OldFI, int NewFI,
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void RewriteInstruction(MachineInstr *MI, int OldFI, int NewFI,
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MachineFunction &MF);
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MachineFunction &MF);
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bool PropagateBackward(MachineBasicBlock::iterator MII,
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MachineBasicBlock *MBB,
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unsigned OldReg, unsigned NewReg);
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bool PropagateForward(MachineBasicBlock::iterator MII,
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MachineBasicBlock *MBB,
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unsigned OldReg, unsigned NewReg);
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void UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
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unsigned Reg, const TargetRegisterClass *RC,
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SmallSet<unsigned, 4> &Defs,
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MachineFunction &MF);
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bool AllMemRefsCanBeUnfolded(int SS);
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bool RemoveDeadStores(MachineBasicBlock* MBB);
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bool RemoveDeadStores(MachineBasicBlock* MBB);
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};
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};
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} // end anonymous namespace
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} // end anonymous namespace
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@ -248,79 +225,6 @@ StackSlotColoring::OverlapWithAssignments(LiveInterval *li, int Color) const {
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return false;
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return false;
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}
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}
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/// ColorSlotsWithFreeRegs - If there are any free registers available, try
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/// replacing spill slots references with registers instead.
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bool
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StackSlotColoring::ColorSlotsWithFreeRegs(SmallVector<int, 16> &SlotMapping,
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SmallVector<SmallVector<int, 4>, 16> &RevMap,
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BitVector &SlotIsReg) {
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if (!(ColorWithRegs || ColorWithRegsOpt) || !VRM->HasUnusedRegisters())
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return false;
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bool Changed = false;
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DEBUG(dbgs() << "Assigning unused registers to spill slots:\n");
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for (unsigned i = 0, e = SSIntervals.size(); i != e; ++i) {
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LiveInterval *li = SSIntervals[i];
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int SS = TargetRegisterInfo::stackSlot2Index(li->reg);
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if (!UsedColors[SS] || li->weight < 20)
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// If the weight is < 20, i.e. two references in a loop with depth 1,
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// don't bother with it.
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continue;
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// These slots allow to share the same registers.
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bool AllColored = true;
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SmallVector<unsigned, 4> ColoredRegs;
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for (unsigned j = 0, ee = RevMap[SS].size(); j != ee; ++j) {
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int RSS = RevMap[SS][j];
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const TargetRegisterClass *RC = LS->getIntervalRegClass(RSS);
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// If it's not colored to another stack slot, try coloring it
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// to a "free" register.
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if (!RC) {
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AllColored = false;
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continue;
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}
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unsigned Reg = VRM->getFirstUnusedRegister(RC);
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if (!Reg) {
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AllColored = false;
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continue;
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}
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if (!AllMemRefsCanBeUnfolded(RSS)) {
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AllColored = false;
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continue;
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} else {
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DEBUG(dbgs() << "Assigning fi#" << RSS << " to "
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<< TRI->getName(Reg) << '\n');
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ColoredRegs.push_back(Reg);
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SlotMapping[RSS] = Reg;
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SlotIsReg.set(RSS);
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Changed = true;
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}
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}
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// Register and its sub-registers are no longer free.
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while (!ColoredRegs.empty()) {
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unsigned Reg = ColoredRegs.back();
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ColoredRegs.pop_back();
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VRM->setRegisterUsed(Reg);
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// If reg is a callee-saved register, it will have to be spilled in
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// the prologue.
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MRI->setPhysRegUsed(Reg);
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
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VRM->setRegisterUsed(*AS);
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MRI->setPhysRegUsed(*AS);
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}
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}
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// This spill slot is dead after the rewrites
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if (AllColored) {
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MFI->RemoveStackObject(SS);
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++NumEliminated;
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}
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}
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DEBUG(dbgs() << '\n');
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return Changed;
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}
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/// ColorSlot - Assign a "color" (stack slot) to the specified stack slot.
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/// ColorSlot - Assign a "color" (stack slot) to the specified stack slot.
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///
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///
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int StackSlotColoring::ColorSlot(LiveInterval *li) {
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int StackSlotColoring::ColorSlot(LiveInterval *li) {
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@ -372,7 +276,6 @@ bool StackSlotColoring::ColorSlots(MachineFunction &MF) {
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SmallVector<int, 16> SlotMapping(NumObjs, -1);
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SmallVector<int, 16> SlotMapping(NumObjs, -1);
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SmallVector<float, 16> SlotWeights(NumObjs, 0.0);
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SmallVector<float, 16> SlotWeights(NumObjs, 0.0);
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SmallVector<SmallVector<int, 4>, 16> RevMap(NumObjs);
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SmallVector<SmallVector<int, 4>, 16> RevMap(NumObjs);
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BitVector SlotIsReg(NumObjs);
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BitVector UsedColors(NumObjs);
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BitVector UsedColors(NumObjs);
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DEBUG(dbgs() << "Color spill slot intervals:\n");
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DEBUG(dbgs() << "Color spill slot intervals:\n");
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@ -404,31 +307,19 @@ bool StackSlotColoring::ColorSlots(MachineFunction &MF) {
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DEBUG(dbgs() << '\n');
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DEBUG(dbgs() << '\n');
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#endif
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#endif
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// Can we "color" a stack slot with a unused register?
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Changed |= ColorSlotsWithFreeRegs(SlotMapping, RevMap, SlotIsReg);
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if (!Changed)
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if (!Changed)
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return false;
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return false;
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// Rewrite all MO_FrameIndex operands.
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// Rewrite all MO_FrameIndex operands.
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SmallVector<SmallSet<unsigned, 4>, 4> NewDefs(MF.getNumBlockIDs());
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SmallVector<SmallSet<unsigned, 4>, 4> NewDefs(MF.getNumBlockIDs());
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for (unsigned SS = 0, SE = SSRefs.size(); SS != SE; ++SS) {
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for (unsigned SS = 0, SE = SSRefs.size(); SS != SE; ++SS) {
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bool isReg = SlotIsReg[SS];
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int NewFI = SlotMapping[SS];
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int NewFI = SlotMapping[SS];
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if (NewFI == -1 || (NewFI == (int)SS && !isReg))
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if (NewFI == -1 || (NewFI == (int)SS))
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continue;
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continue;
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const TargetRegisterClass *RC = LS->getIntervalRegClass(SS);
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SmallVector<MachineInstr*, 8> &RefMIs = SSRefs[SS];
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SmallVector<MachineInstr*, 8> &RefMIs = SSRefs[SS];
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for (unsigned i = 0, e = RefMIs.size(); i != e; ++i)
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for (unsigned i = 0, e = RefMIs.size(); i != e; ++i)
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if (!isReg)
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RewriteInstruction(RefMIs[i], SS, NewFI, MF);
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RewriteInstruction(RefMIs[i], SS, NewFI, MF);
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else {
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// Rewrite to use a register instead.
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unsigned MBBId = RefMIs[i]->getParent()->getNumber();
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SmallSet<unsigned, 4> &Defs = NewDefs[MBBId];
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UnfoldAndRewriteInstruction(RefMIs[i], SS, NewFI, RC, Defs, MF);
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}
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}
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}
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// Delete unused stack slots.
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// Delete unused stack slots.
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@ -441,28 +332,6 @@ bool StackSlotColoring::ColorSlots(MachineFunction &MF) {
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return true;
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return true;
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}
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}
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/// AllMemRefsCanBeUnfolded - Return true if all references of the specified
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/// spill slot index can be unfolded.
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bool StackSlotColoring::AllMemRefsCanBeUnfolded(int SS) {
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SmallVector<MachineInstr*, 8> &RefMIs = SSRefs[SS];
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for (unsigned i = 0, e = RefMIs.size(); i != e; ++i) {
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MachineInstr *MI = RefMIs[i];
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if (TII->isLoadFromStackSlot(MI, SS) ||
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TII->isStoreToStackSlot(MI, SS))
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// Restore and spill will become copies.
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return true;
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if (!TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(), false, false))
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return false;
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for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
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MachineOperand &MO = MI->getOperand(j);
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if (MO.isFI() && MO.getIndex() != SS)
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// If it uses another frameindex, we can, currently* unfold it.
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return false;
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}
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}
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return true;
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}
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/// RewriteInstruction - Rewrite specified instruction by replacing references
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/// RewriteInstruction - Rewrite specified instruction by replacing references
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/// to old frame index with new one.
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/// to old frame index with new one.
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void StackSlotColoring::RewriteInstruction(MachineInstr *MI, int OldFI,
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void StackSlotColoring::RewriteInstruction(MachineInstr *MI, int OldFI,
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@ -489,179 +358,6 @@ void StackSlotColoring::RewriteInstruction(MachineInstr *MI, int OldFI,
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(*I)->setValue(NewSV);
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(*I)->setValue(NewSV);
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}
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}
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/// PropagateBackward - Traverse backward and look for the definition of
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/// OldReg. If it can successfully update all of the references with NewReg,
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/// do so and return true.
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bool StackSlotColoring::PropagateBackward(MachineBasicBlock::iterator MII,
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MachineBasicBlock *MBB,
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unsigned OldReg, unsigned NewReg) {
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if (MII == MBB->begin())
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return false;
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SmallVector<MachineOperand*, 4> Uses;
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SmallVector<MachineOperand*, 4> Refs;
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while (--MII != MBB->begin()) {
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bool FoundDef = false; // Not counting 2address def.
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Uses.clear();
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const MCInstrDesc &MCID = MII->getDesc();
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for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MII->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0)
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continue;
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if (Reg == OldReg) {
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if (MO.isImplicit())
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return false;
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// Abort the use is actually a sub-register def. We don't have enough
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// information to figure out if it is really legal.
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if (MO.getSubReg() || MII->isSubregToReg())
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return false;
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const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI);
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if (RC && !RC->contains(NewReg))
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return false;
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if (MO.isUse()) {
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Uses.push_back(&MO);
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} else {
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Refs.push_back(&MO);
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if (!MII->isRegTiedToUseOperand(i))
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FoundDef = true;
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}
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} else if (TRI->regsOverlap(Reg, NewReg)) {
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return false;
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} else if (TRI->regsOverlap(Reg, OldReg)) {
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if (!MO.isUse() || !MO.isKill())
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return false;
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}
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}
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if (FoundDef) {
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// Found non-two-address def. Stop here.
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for (unsigned i = 0, e = Refs.size(); i != e; ++i)
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Refs[i]->setReg(NewReg);
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return true;
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}
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// Two-address uses must be updated as well.
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for (unsigned i = 0, e = Uses.size(); i != e; ++i)
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Refs.push_back(Uses[i]);
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}
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return false;
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}
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/// PropagateForward - Traverse forward and look for the kill of OldReg. If
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/// it can successfully update all of the uses with NewReg, do so and
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/// return true.
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bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII,
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MachineBasicBlock *MBB,
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unsigned OldReg, unsigned NewReg) {
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if (MII == MBB->end())
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return false;
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SmallVector<MachineOperand*, 4> Uses;
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while (++MII != MBB->end()) {
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bool FoundKill = false;
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const MCInstrDesc &MCID = MII->getDesc();
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for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MII->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0)
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continue;
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if (Reg == OldReg) {
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if (MO.isDef() || MO.isImplicit())
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return false;
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// Abort the use is actually a sub-register use. We don't have enough
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// information to figure out if it is really legal.
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if (MO.getSubReg())
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return false;
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const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI);
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if (RC && !RC->contains(NewReg))
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return false;
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if (MO.isKill())
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FoundKill = true;
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Uses.push_back(&MO);
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} else if (TRI->regsOverlap(Reg, NewReg) ||
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TRI->regsOverlap(Reg, OldReg))
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return false;
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}
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if (FoundKill) {
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for (unsigned i = 0, e = Uses.size(); i != e; ++i)
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Uses[i]->setReg(NewReg);
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return true;
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}
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}
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return false;
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}
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/// UnfoldAndRewriteInstruction - Rewrite specified instruction by unfolding
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/// folded memory references and replacing those references with register
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/// references instead.
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void
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StackSlotColoring::UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
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unsigned Reg,
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const TargetRegisterClass *RC,
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SmallSet<unsigned, 4> &Defs,
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MachineFunction &MF) {
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MachineBasicBlock *MBB = MI->getParent();
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if (unsigned DstReg = TII->isLoadFromStackSlot(MI, OldFI)) {
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if (PropagateForward(MI, MBB, DstReg, Reg)) {
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DEBUG(dbgs() << "Eliminated load: ");
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DEBUG(MI->dump());
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++NumLoadElim;
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} else {
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BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY),
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DstReg).addReg(Reg);
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++NumRegRepl;
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}
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if (!Defs.count(Reg)) {
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// If this is the first use of Reg in this MBB and it wasn't previously
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// defined in MBB, add it to livein.
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||||||
MBB->addLiveIn(Reg);
|
|
||||||
Defs.insert(Reg);
|
|
||||||
}
|
|
||||||
} else if (unsigned SrcReg = TII->isStoreToStackSlot(MI, OldFI)) {
|
|
||||||
if (MI->killsRegister(SrcReg) && PropagateBackward(MI, MBB, SrcReg, Reg)) {
|
|
||||||
DEBUG(dbgs() << "Eliminated store: ");
|
|
||||||
DEBUG(MI->dump());
|
|
||||||
++NumStoreElim;
|
|
||||||
} else {
|
|
||||||
BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY), Reg)
|
|
||||||
.addReg(SrcReg);
|
|
||||||
++NumRegRepl;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Remember reg has been defined in MBB.
|
|
||||||
Defs.insert(Reg);
|
|
||||||
} else {
|
|
||||||
SmallVector<MachineInstr*, 4> NewMIs;
|
|
||||||
bool Success = TII->unfoldMemoryOperand(MF, MI, Reg, false, false, NewMIs);
|
|
||||||
(void)Success; // Silence compiler warning.
|
|
||||||
assert(Success && "Failed to unfold!");
|
|
||||||
MachineInstr *NewMI = NewMIs[0];
|
|
||||||
MBB->insert(MI, NewMI);
|
|
||||||
++NumRegRepl;
|
|
||||||
|
|
||||||
if (NewMI->readsRegister(Reg)) {
|
|
||||||
if (!Defs.count(Reg))
|
|
||||||
// If this is the first use of Reg in this MBB and it wasn't previously
|
|
||||||
// defined in MBB, add it to livein.
|
|
||||||
MBB->addLiveIn(Reg);
|
|
||||||
Defs.insert(Reg);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
MBB->erase(MI);
|
|
||||||
}
|
|
||||||
|
|
||||||
/// RemoveDeadStores - Scan through a basic block and look for loads followed
|
/// RemoveDeadStores - Scan through a basic block and look for loads followed
|
||||||
/// by stores. If they're both using the same stack slot, then the store is
|
/// by stores. If they're both using the same stack slot, then the store is
|
||||||
|
|||||||
@ -1,55 +0,0 @@
|
|||||||
; RUN: llc < %s -mtriple=i386-pc-linux-gnu -disable-fp-elim -color-ss-with-regs | not grep dil
|
|
||||||
; PR4552
|
|
||||||
|
|
||||||
target triple = "i386-pc-linux-gnu"
|
|
||||||
@g_8 = internal global i32 0 ; <i32*> [#uses=1]
|
|
||||||
@g_72 = internal global i32 0 ; <i32*> [#uses=1]
|
|
||||||
@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32, i8, i8)* @uint84 to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
|
|
||||||
|
|
||||||
define i32 @uint84(i32 %p_15, i8 signext %p_17, i8 signext %p_19) nounwind {
|
|
||||||
entry:
|
|
||||||
%g_72.promoted = load i32* @g_72 ; <i32> [#uses=1]
|
|
||||||
%g_8.promoted = load i32* @g_8 ; <i32> [#uses=1]
|
|
||||||
br label %bb
|
|
||||||
|
|
||||||
bb: ; preds = %func_40.exit, %entry
|
|
||||||
%g_8.tmp.1 = phi i32 [ %g_8.promoted, %entry ], [ %g_8.tmp.0, %func_40.exit ] ; <i32> [#uses=3]
|
|
||||||
%g_72.tmp.1 = phi i32 [ %g_72.promoted, %entry ], [ %g_72.tmp.0, %func_40.exit ] ; <i32> [#uses=3]
|
|
||||||
%retval12.i4.i.i = trunc i32 %g_8.tmp.1 to i8 ; <i8> [#uses=2]
|
|
||||||
%0 = trunc i32 %g_72.tmp.1 to i8 ; <i8> [#uses=2]
|
|
||||||
%1 = mul i8 %retval12.i4.i.i, %0 ; <i8> [#uses=1]
|
|
||||||
%2 = icmp eq i8 %1, 0 ; <i1> [#uses=1]
|
|
||||||
br i1 %2, label %bb2.i.i, label %bb.i.i
|
|
||||||
|
|
||||||
bb.i.i: ; preds = %bb
|
|
||||||
%3 = sext i8 %0 to i32 ; <i32> [#uses=1]
|
|
||||||
%4 = and i32 %3, 50295 ; <i32> [#uses=1]
|
|
||||||
%5 = icmp eq i32 %4, 0 ; <i1> [#uses=1]
|
|
||||||
br i1 %5, label %bb2.i.i, label %func_55.exit.i
|
|
||||||
|
|
||||||
bb2.i.i: ; preds = %bb.i.i, %bb
|
|
||||||
br label %func_55.exit.i
|
|
||||||
|
|
||||||
func_55.exit.i: ; preds = %bb2.i.i, %bb.i.i
|
|
||||||
%g_72.tmp.2 = phi i32 [ 1, %bb2.i.i ], [ %g_72.tmp.1, %bb.i.i ] ; <i32> [#uses=1]
|
|
||||||
%6 = phi i32 [ 1, %bb2.i.i ], [ %g_72.tmp.1, %bb.i.i ] ; <i32> [#uses=1]
|
|
||||||
%7 = trunc i32 %6 to i8 ; <i8> [#uses=2]
|
|
||||||
%8 = mul i8 %7, %retval12.i4.i.i ; <i8> [#uses=1]
|
|
||||||
%9 = icmp eq i8 %8, 0 ; <i1> [#uses=1]
|
|
||||||
br i1 %9, label %bb2.i4.i, label %bb.i3.i
|
|
||||||
|
|
||||||
bb.i3.i: ; preds = %func_55.exit.i
|
|
||||||
%10 = sext i8 %7 to i32 ; <i32> [#uses=1]
|
|
||||||
%11 = and i32 %10, 50295 ; <i32> [#uses=1]
|
|
||||||
%12 = icmp eq i32 %11, 0 ; <i1> [#uses=1]
|
|
||||||
br i1 %12, label %bb2.i4.i, label %func_40.exit
|
|
||||||
|
|
||||||
bb2.i4.i: ; preds = %bb.i3.i, %func_55.exit.i
|
|
||||||
br label %func_40.exit
|
|
||||||
|
|
||||||
func_40.exit: ; preds = %bb2.i4.i, %bb.i3.i
|
|
||||||
%g_72.tmp.0 = phi i32 [ 1, %bb2.i4.i ], [ %g_72.tmp.2, %bb.i3.i ] ; <i32> [#uses=1]
|
|
||||||
%phitmp = icmp sgt i32 %g_8.tmp.1, 0 ; <i1> [#uses=1]
|
|
||||||
%g_8.tmp.0 = select i1 %phitmp, i32 %g_8.tmp.1, i32 1 ; <i32> [#uses=1]
|
|
||||||
br label %bb
|
|
||||||
}
|
|
||||||
Loading…
x
Reference in New Issue
Block a user