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ARM CPS mode immediate is 5 bits, not 4.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136505 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-07-29 20:02:39 +00:00
parent 6e8bb8a0cb
commit 33768dba54
1 changed files with 2 additions and 2 deletions
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4
lib/Target/ARM/ARMInstrInfo.td
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@ -1319,13 +1319,13 @@ class CPS<dag iops, string asm_ops>
}
let M = 1 in
def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_15:$mode),
def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
"$imod\t$iflags, $mode">;
let mode = 0, M = 0 in
def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
let imod = 0, iflags = 0, M = 1 in
def CPS1p : CPS<(ins imm0_15:$mode), "\t$mode">;
def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
// Preload signals the memory system of possible future data/instruction access.
// These are for disassembly only.