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R600/SI: Prettier display of input modifiers

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208479 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune 2014-05-10 19:18:33 +00:00
parent d19e830174
commit 3378ca7d5c
10 changed files with 82 additions and 41 deletions
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12
lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
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@ -158,6 +158,18 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
}
}
void AMDGPUInstPrinter::printOperandAndMods(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
unsigned InputModifiers = MI->getOperand(OpNo).getImm();
if (InputModifiers & 0x1)
O << "-";
if (InputModifiers & 0x2)
O << "|";
printOperand(MI, OpNo + 1, O);
if (InputModifiers & 0x2)
O << "|";
}
void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNum).getImm();

1
lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
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@ -38,6 +38,7 @@ private:
void printRegOperand(unsigned RegNo, raw_ostream &O);
void printImmediate(uint32_t Imm, raw_ostream &O);
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printOperandAndMods(const MCInst *MI, unsigned OpNo, raw_ostream &O);
static void printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,

16
lib/Target/R600/SIISelLowering.cpp
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@ -576,12 +576,12 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
MI->getOperand(0).getReg())
.addImm(0) // SRC0 modifiers
.addOperand(MI->getOperand(1))
.addImm(0) // SRC1 modifiers
.addImm(0) // SRC1
.addImm(0) // ABS
.addImm(1) // CLAMP
.addImm(0) // OMOD
.addImm(0); // NEG
.addImm(0); // OMOD
MI->eraseFromParent();
}
}
@ -1325,7 +1325,6 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? nullptr : &TII->get(OpcodeE64);
assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
assert(!DescE64 || DescE64->getNumOperands() == (NumOps + 4));
int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
bool HaveVSrc = false, HaveSSrc = false;
@ -1422,8 +1421,15 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
}
if (Promote2e64) {
std::vector<SDValue> OldOps(Ops);
Ops.clear();
for (unsigned i = 0; i < OldOps.size(); ++i) {
// src_modifier
Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
Ops.push_back(OldOps[i]);
}
// Add the modifier flags while promoting
for (unsigned i = 0; i < 4; ++i)
for (unsigned i = 0; i < 2; ++i)
Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
}

21
lib/Target/R600/SIInstrFormats.td
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@ -210,16 +210,19 @@ class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
Enc64 <outs, ins, asm, pattern> {
bits<8> dst;
bits<2> src0_modifiers;
bits<9> src0;
bits<2> src1_modifiers;
bits<9> src1;
bits<2> src2_modifiers;
bits<9> src2;
bits<3> abs;
bits<1> clamp;
bits<2> omod;
bits<3> neg;
let Inst{7-0} = dst;
let Inst{10-8} = abs;
let Inst{8} = src0_modifiers{1};
let Inst{9} = src1_modifiers{1};
let Inst{10} = src2_modifiers{1};
let Inst{11} = clamp;
let Inst{25-17} = op;
let Inst{31-26} = 0x34; //encoding
@ -227,7 +230,9 @@ class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
let Inst{49-41} = src1;
let Inst{58-50} = src2;
let Inst{60-59} = omod;
let Inst{63-61} = neg;
let Inst{61} = src0_modifiers{0};
let Inst{62} = src1_modifiers{0};
let Inst{63} = src2_modifiers{0};
let mayLoad = 0;
let mayStore = 0;
@ -240,12 +245,14 @@ class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
Enc64 <outs, ins, asm, pattern> {
bits<8> dst;
bits<2> src0_modifiers;
bits<9> src0;
bits<2> src1_modifiers;
bits<9> src1;
bits<2> src2_modifiers;
bits<9> src2;
bits<7> sdst;
bits<2> omod;
bits<3> neg;
let Inst{7-0} = dst;
let Inst{14-8} = sdst;
@ -255,7 +262,9 @@ class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
let Inst{49-41} = src1;
let Inst{58-50} = src2;
let Inst{60-59} = omod;
let Inst{63-61} = neg;
let Inst{61} = src0_modifiers{0};
let Inst{62} = src1_modifiers{0};
let Inst{63} = src2_modifiers{0};
let mayLoad = 0;
let mayStore = 0;

11
lib/Target/R600/SIInstrInfo.cpp
View File

@ -1188,6 +1188,10 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
// We are converting these to a BFE, so we need to add the missing
// operands for the size and offset.
unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
Inst->addOperand(Inst->getOperand(1));
Inst->getOperand(1).ChangeToImmediate(0);
Inst->addOperand(MachineOperand::CreateImm(0));
Inst->addOperand(MachineOperand::CreateImm(0));
Inst->addOperand(MachineOperand::CreateImm(0));
Inst->addOperand(MachineOperand::CreateImm(Size));
@ -1195,8 +1199,6 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
// 3 to not hit an assertion later in MCInstLower.
Inst->addOperand(MachineOperand::CreateImm(0));
Inst->addOperand(MachineOperand::CreateImm(0));
Inst->addOperand(MachineOperand::CreateImm(0));
Inst->addOperand(MachineOperand::CreateImm(0));
}
addDescImplicitUseDef(NewDesc, Inst);
@ -1213,10 +1215,11 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
Inst->RemoveOperand(2); // Remove old immediate.
Inst->addOperand(Inst->getOperand(1));
Inst->getOperand(1).ChangeToImmediate(0);
Inst->addOperand(MachineOperand::CreateImm(Offset));
Inst->addOperand(MachineOperand::CreateImm(BitWidth));
Inst->addOperand(MachineOperand::CreateImm(0));
Inst->addOperand(MachineOperand::CreateImm(BitWidth));
Inst->addOperand(MachineOperand::CreateImm(0));
Inst->addOperand(MachineOperand::CreateImm(0));
Inst->addOperand(MachineOperand::CreateImm(0));

46
lib/Target/R600/SIInstrInfo.td
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@ -245,6 +245,11 @@ class VOP2_REV <string revOp, bit isOrig> {
bit IsOrig = isOrig;
}
// This must always be right before the operand being input modified.
def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
let PrintMethod = "printOperandAndMods";
}
multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
string opName, list<dag> pattern> {
@ -256,10 +261,8 @@ multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
def _e64 : VOP3 <
{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
(outs drc:$dst),
(ins src:$src0,
i32imm:$abs, i32imm:$clamp,
i32imm:$omod, i32imm:$neg),
opName#"_e64 $dst, $src0, $abs, $clamp, $omod, $neg", []
(ins InputMods:$src0_modifiers, src:$src0, i32imm:$clamp, i32imm:$omod),
opName#"_e64 $dst, $src0_modifiers, $clamp, $omod", []
>, VOP <opName> {
let src1 = SIOperand.ZERO;
let src2 = SIOperand.ZERO;
@ -288,10 +291,10 @@ multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
def _e64 : VOP3 <
{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
(outs vrc:$dst),
(ins arc:$src0, arc:$src1,
i32imm:$abs, i32imm:$clamp,
i32imm:$omod, i32imm:$neg),
opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
(ins InputMods:$src0_modifiers, arc:$src0,
InputMods:$src1_modifiers, arc:$src1,
i32imm:$clamp, i32imm:$omod),
opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod", []
>, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
let src2 = SIOperand.ZERO;
}
@ -316,10 +319,10 @@ multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern,
def _e64 : VOP3b <
{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
(outs VReg_32:$dst),
(ins VSrc_32:$src0, VSrc_32:$src1,
i32imm:$abs, i32imm:$clamp,
i32imm:$omod, i32imm:$neg),
opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
(ins InputMods: $src0_modifiers, VSrc_32:$src0,
InputMods:$src1_modifiers, VSrc_32:$src1,
i32imm:$clamp, i32imm:$omod),
opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod", []
>, VOP <opName>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
let src2 = SIOperand.ZERO;
/* the VOP2 variant puts the carry out into VCC, the VOP3 variant
@ -340,15 +343,16 @@ multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
def _e64 : VOP3 <
{0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
(outs SReg_64:$dst),
(ins arc:$src0, arc:$src1,
InstFlag:$abs, InstFlag:$clamp,
InstFlag:$omod, InstFlag:$neg),
opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg",
(ins InputMods:$src0_modifiers, arc:$src0,
InputMods:$src1_modifiers, arc:$src1,
InstFlag:$clamp, InstFlag:$omod),
opName#"_e64 $dst, $src0_modifiers, $src1_modifiers, $clamp, $omod",
!if(!eq(!cast<string>(cond), "COND_NULL"), []<dag>,
[(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), arc:$src1, cond)))]
)
>, VOP <opName> {
let src2 = SIOperand.ZERO;
let src2_modifiers = 0;
}
}
@ -362,9 +366,10 @@ multiclass VOPC_64 <bits<8> op, string opName,
class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
op, (outs VReg_32:$dst),
(ins VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2,
InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
(ins InputMods: $src0_modifiers, VSrc_32:$src0, InputMods:$src1_modifiers,
VSrc_32:$src1, InputMods:$src2_modifiers, VSrc_32:$src2,
InstFlag:$clamp, InstFlag:$omod),
opName#" $dst, $src0_modifiers, $src1, $src2, $clamp, $omod", pattern
>, VOP <opName>;
class VOP3_64_Shift <bits <9> op, string opName, list<dag> pattern> : VOP3 <
@ -374,10 +379,9 @@ class VOP3_64_Shift <bits <9> op, string opName, list<dag> pattern> : VOP3 <
>, VOP <opName> {
let src2 = SIOperand.ZERO;
let abs = 0;
let src0_modifiers = 0;
let clamp = 0;
let omod = 0;
let neg = 0;
}
class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <

8
lib/Target/R600/SIInstructions.td
View File

@ -1115,7 +1115,11 @@ def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
"V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
[(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
>;
> {
let src0_modifiers = 0;
let src1_modifiers = 0;
let src2_modifiers = 0;
}
//f32 pattern for V_CNDMASK_B32_e64
def : Pat <
@ -2138,7 +2142,7 @@ def : Pat <
def : Pat <
(int_SI_tid),
(V_MBCNT_HI_U32_B32_e32 0xffffffff,
(V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0, 0, 0))
(V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0))
>;
/********** ================== **********/

2
test/CodeGen/R600/fneg.ll
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@ -51,7 +51,7 @@ entry:
; R600-CHECK: -KC0[2].Z
; SI-CHECK-LABEL: @fneg_free
; XXX: We could use V_ADD_F32_e64 with the negate bit here instead.
; SI-CHECK: V_SUB_F32_e64 v{{[0-9]}}, 0.000000e+00, s{{[0-9]}}, 0, 0, 0, 0
; SI-CHECK: V_SUB_F32_e64 v{{[0-9]}}, 0.000000e+00, s{{[0-9]}}, 0, 0
define void @fneg_free(float addrspace(1)* %out, i32 %in) {
entry:
%0 = bitcast i32 %in to float

3
test/CodeGen/R600/seto.ll
View File

@ -1,6 +1,7 @@
;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: V_CMP_O_F32_e64 s[0:1], {{[sv][0-9]+, [sv][0-9]+}}, 0, 0, 0, 0
;CHECK-LABEL: @main
;CHECK: V_CMP_O_F32_e64 s[0:1], {{[sv][0-9]+, [sv][0-9]+}}, 0, 0
define void @main(float %p) {
main_body:

3
test/CodeGen/R600/setuo.ll
View File

@ -1,6 +1,7 @@
;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
;CHECK: V_CMP_U_F32_e64 s[0:1], {{[sv][0-9]+, [sv][0-9]+}}, 0, 0, 0, 0
;CHECK-LABEL: @main
;CHECK: V_CMP_U_F32_e64 s[0:1], {{[sv][0-9]+, [sv][0-9]+}}, 0, 0
define void @main(float %p) {
main_body: