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https://github.com/c64scene-ar/llvm-6502.git
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fix FCMOVxx typo, set rem and div to hardcode target reg to be the same as the one the assembler uese, update ISel to put values in regs used by assembler for rem and div
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20434 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
2f3c9b7562
commit
3381913322
@ -49,6 +49,7 @@ namespace {
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addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
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setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
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setOperationAction(ISD::EXTLOAD , MVT::f32 , Promote);
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setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::ZEXTLOAD , MVT::i32 , Expand);
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@ -64,6 +65,7 @@ namespace {
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setOperationAction(ISD::MEMSET , MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
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//Doesn't work yet
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setOperationAction(ISD::SETCC , MVT::f32, Promote);
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computeRegisterProperties();
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@ -557,7 +559,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLE : Alpha::FCMOVGE; break;
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case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQ : Alpha::FCMOVNE; break;
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}
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BuildMI(BB, Opc, 3, Result).addReg(TV).addReg(FV).addReg(Tmp3);
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BuildMI(BB, Opc, 3, Result).addReg(FV).addReg(TV).addReg(Tmp3);
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return Result;
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}
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else
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@ -843,11 +845,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
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BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R30).addReg(Alpha::R30);
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return Result;
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case ISD::ConstantPool:
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Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addConstantPoolIndex(Tmp1);
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return Result;
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// case ISD::ConstantPool:
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// Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
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// AlphaLowering.restoreGP(BB);
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// BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addConstantPoolIndex(Tmp1);
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// return Result;
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case ISD::FrameIndex:
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BuildMI(BB, Alpha::LDA, 2, Result)
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@ -1393,8 +1395,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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//set up regs explicitly (helps Reg alloc)
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BuildMI(BB, Alpha::BIS, 2, Alpha::R24).addReg(Tmp1).addReg(Tmp1);
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BuildMI(BB, Alpha::BIS, 2, Alpha::R25).addReg(Tmp2).addReg(Tmp2);
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AlphaLowering.restoreGP(BB);
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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BuildMI(BB, Opc, 2).addReg(Alpha::R24).addReg(Alpha::R25);
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BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R27).addReg(Alpha::R27);
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return Result;
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case ISD::FP_TO_UINT:
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@ -79,13 +79,15 @@ let Uses = [R29, R28] in {
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def STT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "stt $RA,$DISP">; //store double
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}
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//RESULTS of these go to R27
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let Uses = [R29],
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Defs = [R28, R29, R23, R24, R25, R27] in
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Defs = [R28, R23, R24, R25, R27] in
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{
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def REMQU : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "remqu $RA,$RB,$RC">; //unsigned remander
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def REMQ : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "remq $RA,$RB,$RC">; //signed remander
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def DIVQU : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "divqu $RA,$RB,$RC">; //unsigned division
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def DIVQ : PseudoInstAlpha<(ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "divq $RA,$RB,$RC">; //signed division
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def REMQU : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "remqu $RA,$RB,$$27">; //unsigned remander
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def REMQ : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "remq $RA,$RB,$$27">; //signed remander
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def DIVQU : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "divqu $RA,$RB,$$27">; //unsigned division
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def DIVQ : PseudoInstAlpha<(ops GPRC:$RA, GPRC:$RB), "divq $RA,$RB,$$27">; //signed division
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}
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//***********************
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@ -96,31 +98,52 @@ let Uses = [R29],
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let isTwoAddress = 1 in {
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//conditional moves, int
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def CMOVEQ : OForm< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "cmoveq $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND = zero
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def CMOVEQi : OFormL< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "cmoveq $RCOND,$L,$RDEST">; //CMOVE if RCOND = zero
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def CMOVGE : OForm< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "CMOVGE $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND >= zero
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def CMOVGEi : OFormL< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "CMOVGE $RCOND,$L,$RDEST">; //CMOVE if RCOND >= zero
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def CMOVGT : OForm< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "CMOVGT $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND > zero
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def CMOVGTi : OFormL< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "CMOVGT $RCOND,$L,$RDEST">; //CMOVE if RCOND > zero
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def CMOVLBC : OForm< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "CMOVLBC $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit clear
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def CMOVLBCi : OFormL< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "CMOVLBC $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit clear
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def CMOVLBS : OForm< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "CMOVLBS $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit set
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def CMOVLBSi : OFormL< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "CMOVLBS $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit set
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def CMOVLE : OForm< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "CMOVLE $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND <= zero
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def CMOVLEi : OFormL< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "CMOVLE $RCOND,$L,$RDEST">; //CMOVE if RCOND <= zero
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def CMOVLT : OForm< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "CMOVLT $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND < zero
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def CMOVLTi : OFormL< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "CMOVLT $RCOND,$L,$RDEST">; //CMOVE if RCOND < zero
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def CMOVNE : OForm< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND), "cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND != zero
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def CMOVNEi : OFormL< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND), "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
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def CMOVEQ : OForm< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"cmoveq $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND = zero
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def CMOVEQi : OFormL< 0x11, 0x24, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"cmoveq $RCOND,$L,$RDEST">; //CMOVE if RCOND = zero
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def CMOVGE : OForm< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"CMOVGE $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND >= zero
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def CMOVGEi : OFormL< 0x11, 0x46, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"CMOVGE $RCOND,$L,$RDEST">; //CMOVE if RCOND >= zero
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def CMOVGT : OForm< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"CMOVGT $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND > zero
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def CMOVGTi : OFormL< 0x11, 0x66, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"CMOVGT $RCOND,$L,$RDEST">; //CMOVE if RCOND > zero
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def CMOVLBC : OForm< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"CMOVLBC $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit clear
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def CMOVLBCi : OFormL< 0x11, 0x16, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"CMOVLBC $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit clear
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def CMOVLBS : OForm< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"CMOVLBS $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND low bit set
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def CMOVLBSi : OFormL< 0x11, 0x14, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"CMOVLBS $RCOND,$L,$RDEST">; //CMOVE if RCOND low bit set
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def CMOVLE : OForm< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"CMOVLE $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND <= zero
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def CMOVLEi : OFormL< 0x11, 0x64, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"CMOVLE $RCOND,$L,$RDEST">; //CMOVE if RCOND <= zero
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def CMOVLT : OForm< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"CMOVLT $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND < zero
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def CMOVLTi : OFormL< 0x11, 0x44, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"CMOVLT $RCOND,$L,$RDEST">; //CMOVE if RCOND < zero
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def CMOVNE : OForm< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, GPRC:$RSRC, GPRC:$RCOND),
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"cmovne $RCOND,$RSRC,$RDEST">; //CMOVE if RCOND != zero
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def CMOVNEi : OFormL< 0x11, 0x26, (ops GPRC:$RDEST, GPRC:$RSRC2, u8imm:$L, GPRC:$RCOND),
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"cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero
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//conditional moves, fp
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def FCMOVEQ : FPForm<0x17, 0x02A, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmoveq $RCOND,$RSRC,$RDEST">; //FCMOVE if = zero
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def FCMOVGE : FPForm<0x17, 0x02D, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovge $RCOND,$RSRC,$RDEST">; //FCMOVE if >= zero
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def FCMOVGT : FPForm<0x17, 0x02F, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovge $RCOND,$RSRC,$RDEST">; //FCMOVE if > zero
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def FCMOVLE : FPForm<0x17, 0x02E, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovle $RCOND,$RSRC,$RDEST">; //FCMOVE if <= zero
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def FCMOVLT : FPForm<0x17, 0x02, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovlt $RCOND,$RSRC,$RDEST">; // FCMOVE if < zero
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def FCMOVNE : FPForm<0x17, 0x02B, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero
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def FCMOVEQ : FPForm<0x17, 0x02A, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmoveq $RCOND,$RSRC,$RDEST">; //FCMOVE if = zero
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def FCMOVGE : FPForm<0x17, 0x02D, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovge $RCOND,$RSRC,$RDEST">; //FCMOVE if >= zero
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def FCMOVGT : FPForm<0x17, 0x02F, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovgt $RCOND,$RSRC,$RDEST">; //FCMOVE if > zero
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def FCMOVLE : FPForm<0x17, 0x02E, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovle $RCOND,$RSRC,$RDEST">; //FCMOVE if <= zero
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def FCMOVLT : FPForm<0x17, 0x02, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovlt $RCOND,$RSRC,$RDEST">; // FCMOVE if < zero
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def FCMOVNE : FPForm<0x17, 0x02B, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND),
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"fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero
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}
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def ADDL : OForm< 0x10, 0x00, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "addl $RA,$RB,$RC">; //Add longword
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@ -218,6 +241,7 @@ def SLi : OFormL<0x12, 0x39, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "SLL $RA,$
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def SRA : OForm< 0x12, 0x3C, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "SRA $RA,$RB,$RC">; //Shift right arithmetic
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def SRAi : OFormL<0x12, 0x3C, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "SRA $RA,$L,$RC">; //Shift right arithmetic
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def SRL : OForm< 0x12, 0x34, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "SRL $RA,$RB,$RC">; //Shift right logical
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def SRLi : OFormL<0x12, 0x34, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "SRL $RA,$L,$RC">; //Shift right logical
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def SUBL : OForm< 0x10, 0x09, (ops GPRC:$RC, GPRC:$RA, GPRC:$RB), "SUBL $RA,$RB,$RC">; //Subtract longword
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def SUBLi : OFormL<0x10, 0x09, (ops GPRC:$RC, GPRC:$RA, u8imm:$L), "SUBL $RA,$L,$RC">; //Subtract longword
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