*** empty log message ***

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@411 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/Sparc.h

@@ -14,6 +14,7 @@
 
 #include <sys/types.h>
 #include "llvm/CodeGen/TargetMachine.h"
+#include "llvm/Type.h"
 
 // OpCodeMask definitions for the Sparc V9
 // 
@@ -831,7 +832,9 @@ const MachineInstrDescriptor SparcMachineInstrDesc[] = {
   
   // Synthetic phi operation for near-SSA form of machine code
   // Number of operands is variable, indicated by -1.  Result is the first op.
+
   { "PHI",	-1,  0,  0,  false, 0, 0, SPARC_INV,  M_DUMMY_PHI_FLAG },
+
 };
 
 
@@ -860,8 +863,86 @@ public:
     // 2 other groups, including NOPs if necessary).
     return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
   }
+
 };
 
+//---------------------------------------------------------------------------
+// class UltraSparcInstrInfo 
+// 
+// Purpose:
+//   This class provides info about sparc register classes.
+//---------------------------------------------------------------------------
+
+#include "llvm/CodeGen/SparcRegInfo.h"
+
+class LiveRange;
+class UltraSparc;
+
+
+class UltraSparcRegInfo : public MachineRegInfo
+{
+
+ private:
+  enum RegClassIDs { IntRegClassID, FloatRegClassID, FloatCCREgClassID };
+
+  // reverse pointer to get info about the ultra sparc machine
+  const UltraSparc *const UltraSparcInfo;
+
+  // Int arguments can be passed in 6 int regs - %o0 to %o5 (cannot be changed)
+  unsigned const NumOfIntArgRegs;
+
+  // Float arguments can be passed in this many regs - can be canged if needed
+  // %f0 - %f5 are used (can hold 6 floats or 3 doubles)
+  unsigned const NumOfFloatArgRegs;
+
+  void setCallArgColor(LiveRange *const LR, const unsigned RegNo) const;
+
+
+ public:
+
+  UltraSparcRegInfo(const UltraSparc *USI ) : UltraSparcInfo(USI), 
+					      NumOfIntArgRegs(6), 
+					      NumOfFloatArgRegs(6) 
+  {    
+
+    MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
+    MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
+
+    assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 6 && 
+	    "6 Float regs are used for float arg passing");
+
+  }
+
+  inline const UltraSparc & getUltraSparcInfo() const { 
+    return *UltraSparcInfo;
+  }
+
+  inline unsigned getRegClassIDOfValue (const Value *const Val) const {
+    Type::PrimitiveID ty = (Val->getType())->getPrimitiveID();
+    
+    if( ty && ty <= Type::LongTyID || (ty == Type::PointerTyID) )  
+      return IntRegClassID;             // sparc int reg (ty=0: void)
+    else if( ty <= Type::DoubleTyID)
+      return FloatRegClassID;           // sparc float reg class
+    else { 
+      cout << "TypeID: " << ty << endl;
+      assert(0 && "Cannot resolve register class for type");
+
+    }
+  }
+ 
+  void colorArgs(const Method *const Meth, LiveRangeInfo& LRI) const;
+
+  static void printReg(const LiveRange *const LR);
+
+  void colorCallArgs(vector<const Instruction *> & CallInstrList, 
+		     LiveRangeInfo& LRI ) const;
+
+};
+
+
+
+
 
 //---------------------------------------------------------------------------
 // class UltraSparcMachine 
@@ -880,6 +961,9 @@ public:
 };
 
 
+
+
+
 /*---------------------------------------------------------------------------
 Scheduling guidelines for SPARC IIi:
 

include/llvm/CodeGen/SparcRegInfo.h

@@ -0,0 +1,169 @@
+/* Title:   SparcRegClassInfo.h
+   Author:  Ruchira Sasanka
+   Date:    Aug 20, 01
+   Purpose: Contains the description of integer register class of Sparc
+*/
+
+
+#ifndef SPARC_INT_REG_CLASS_H
+#define SPARC_INT_REG_CLASS_H
+
+
+#include "llvm/CodeGen/TargetMachine.h"
+#include <string>
+
+
+//-----------------------------------------------------------------------------
+// Integer Register Class
+//-----------------------------------------------------------------------------
+
+
+// Int register names in same order as enum in class SparcIntRegOrder
+
+static string const IntRegNames[] = 
+  {       "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+    "o0", "o1", "o2", "o3", "o4", "o5",       "o7",
+    "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+    "i0", "i1", "i2", "i3", "i4", "i5", 
+    "g0", "i6", "i7",  "o6" }; 
+
+
+
+class SparcIntRegOrder{ 
+
+ public:
+
+  enum RegsInPrefOrder   // colors possible for a LR (in preferred order)
+   { 
+     // --- following colors are volatile across function calls
+     // %g0 can't be used for coloring - always 0
+                     
+     g1, g2, g3, g4, g5, g6, g7,  //%g1-%g7  
+     o0, o1, o2, o3, o4, o5, o7,  // %o0-%o5, 
+
+     // %o6 is sp, 
+     // all %0's can get modified by a call
+
+     // --- following colors are NON-volatile across function calls
+      
+     l0, l1, l2, l3, l4, l5, l6, l7,    //  %l0-%l7
+     i0, i1, i2, i3, i4, i5,            // %i0-%i5: i's need not be preserved 
+      
+     // %i6 is the fp - so not allocated
+     // %i7 is the ret address - can be used if saved
+
+     // max # of colors reg coloring  can allocate (NumOfAvailRegs)
+
+     // --- following colors are not available for allocation within this phase
+     // --- but can appear for pre-colored ranges 
+
+     g0, i6, i7,  o6,   
+
+     NumOfAllRegs   // place holder to count all possilbe colors
+
+   };
+
+  // max # of colors reg coloring  can allocate
+  static unsigned int const NumOfAvailRegs = g0;
+
+  static unsigned int const StartOfNonVolatileRegs = l0;
+  static unsigned int const StartOfAllRegs = g1;
+
+
+  static const string  getRegName(const unsigned reg) {
+    assert( reg < NumOfAllRegs );
+    return IntRegNames[reg];
+  }
+
+};
+
+
+
+class SparcIntRegClass : public MachineRegClassInfo
+{
+ public:
+
+  SparcIntRegClass(unsigned ID) 
+    : MachineRegClassInfo(0, 
+			  SparcIntRegOrder::NumOfAvailRegs,
+			  SparcIntRegOrder::NumOfAllRegs)
+    {  }
+
+  void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const;
+
+};
+
+//-----------------------------------------------------------------------------
+// Float Register Class
+//-----------------------------------------------------------------------------
+
+static string const FloatRegNames[] = 
+  {    
+    "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",  "f8",  "f9", 
+    "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
+    "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
+    "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
+    "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
+    "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
+    "f60", "f61", "f62", "f63"
+  };
+
+
+class SparcFloatRegOrder{ 
+
+ public:
+
+  enum RegsInPrefOrder {
+
+    f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, 
+    f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
+    f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
+    f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
+    f40, f41, f42, f43, f44, f45, f46, f47, f48, f49,
+    f50, f51, f52, f53, f54, f55, f56, f57, f58, f59,
+    f60, f61, f62, f63
+
+  };
+
+  // there are 64 regs alltogether but only 32 regs can be allocated at
+  // a time.
+
+  static unsigned int const NumOfAvailRegs = 32;
+  static unsigned int const NumOfAllRegs = 64;
+
+  static unsigned int const StartOfNonVolatileRegs = f6;
+  static unsigned int const StartOfAllRegs = f0;
+
+
+  static const string  getRegName(const unsigned reg) {
+    assert( reg < NumOfAllRegs );
+    return FloatRegNames[reg];
+  }
+
+
+
+};
+
+
+class SparcFloatRegClass : public MachineRegClassInfo
+{
+ private:
+
+  int findFloatColor(const IGNode *const Node, unsigned Start,
+		     unsigned End, bool IsColorUsedArr[] ) const;
+
+ public:
+
+  SparcFloatRegClass(unsigned ID) 
+    : MachineRegClassInfo(1, 
+			  SparcFloatRegOrder::NumOfAvailRegs,
+			  SparcFloatRegOrder::NumOfAllRegs)
+    {  }
+
+  void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const;
+
+};
+
+
+
+#endif

include/llvm/CodeGen/TargetMachine.h

@@ -223,6 +223,7 @@ public:
   bool		isDummyPhiInstr		(MachineOpCode opCode) const {
     return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
   }
+
   
   // 
   // Check if an instruction can be issued before its operands are ready,
@@ -628,6 +629,103 @@ protected:
 };
 
 
+
+//-----------------------------------------------------------------------------
+// class MachineRegClassInfo
+// 
+// Purpose:
+//   Interface to description of machine register class (e.g., int reg class
+//   float reg class etc)
+// 
+//--------------------------------------------------------------------------
+
+class IGNode;
+
+
+class MachineRegClassInfo {
+
+protected:
+  
+  const unsigned RegClassID;        // integer ID of a reg class
+  const unsigned NumOfAvailRegs;    // # of avail for coloring -without SP etc.
+  const unsigned NumOfAllRegs;      // # of all registers -including SP,g0 etc.
+
+public:
+  
+  inline unsigned getRegClassID() const { return RegClassID; }
+  inline unsigned getNumOfAvailRegs() const { return NumOfAvailRegs; }
+  inline unsigned getNumOfAllRegs() const { return NumOfAllRegs; }
+
+
+
+  // This method should find a color which is not used by neighbors
+  // (i.e., a false position in IsColorUsedArr) and 
+  virtual void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const = 0;
+
+
+  MachineRegClassInfo(const unsigned ID, const unsigned NVR, 
+		      const unsigned NAR): RegClassID(ID), NumOfAvailRegs(NVR),
+                                           NumOfAllRegs(NAR)
+  { }                         // empty constructor
+
+};
+
+
+
+
+//---------------------------------------------------------------------------
+// class MachineRegInfo
+// 
+// Purpose:
+//   Interface to register info of target machine
+// 
+//--------------------------------------------------------------------------
+
+class Value;
+class LiveRangeInfo;
+class Method;
+class Instruction;
+
+// A vector of all machine register classes
+typedef vector<const MachineRegClassInfo *> MachineRegClassArrayType;
+
+
+class MachineRegInfo : public NonCopyableV {
+
+protected:
+
+  MachineRegClassArrayType MachineRegClassArr;    
+
+  
+public:
+
+
+  inline unsigned int getNumOfRegClasses() const { 
+    return MachineRegClassArr.size(); 
+  }  
+
+  const MachineRegClassInfo *const getMachineRegClass(unsigned i) const { 
+    return MachineRegClassArr[i]; 
+  }
+
+
+  virtual unsigned getRegClassIDOfValue (const Value *const Val) const = 0;
+
+  virtual void colorArgs(const Method *const Meth, 
+			 LiveRangeInfo & LRI) const = 0;
+
+  virtual void colorCallArgs(vector<const Instruction *> & CallInstrList, 
+		     LiveRangeInfo& LRI ) const = 0 ;
+
+
+  MachineRegInfo() { }
+
+};
+
+
+
+
+
 //---------------------------------------------------------------------------
 // class TargetMachine
 // 
@@ -653,10 +751,10 @@ public:
 			 unsigned char DoubleAl = 8, unsigned char FloatAl = 4,
 			 unsigned char LongAl = 8, unsigned char IntAl = 4,
 			 unsigned char ShortAl = 2, unsigned char ByteAl = 1)
-    : TargetName(targetname), DataLayout(targetname, PtrSize, PtrAl,
-					 DoubleAl, FloatAl, LongAl, IntAl,
-					 ShortAl, ByteAl)
-				    {}
+                         : TargetName(targetname), 
+                           DataLayout(targetname, PtrSize, PtrAl,
+				      DoubleAl, FloatAl, LongAl, IntAl, 
+				      ShortAl, ByteAl) { }
   
   /*dtor*/ virtual ~TargetMachine() {}
   
@@ -672,11 +770,15 @@ public:
     return (regNum1 == regNum2);
   }
   
+  const MachineRegInfo& getRegInfo() const { return *machineRegInfo; }
+
 protected:
   // Description of machine instructions
   // Protect so that subclass can control alloc/dealloc
   MachineInstrInfo* machineInstrInfo;
   MachineSchedInfo* machineSchedInfo;
+  const MachineRegInfo* machineRegInfo;
+
 };
 
 //**************************************************************************/