From 33efedc0481c4b0d9866ff526eb1161372b5919f Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Wed, 3 Jul 2013 17:59:07 +0000 Subject: [PATCH] [PowerPC] Use mtocrf when available Just as with mfocrf, it is also preferable to use mtocrf instead of mtcrf when only a single CR register is to be written. Current code however always emits mtcrf. This probably does not matter when using an external assembler, since the GNU assembler will in fact automatically replace mtcrf with mtocrf when possible. It does create inefficient code with the integrated assembler, however. To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and uses those instead of MTCRF/MTCRF8 everything. Just as done in the MFOCRF patch committed as 185556, these patterns will be converted back to MTCRF if MTOCRF is not available on the machine. As a side effect, this allows to modify the MTCRF pattern to accept the full range of mask operands for the benefit of the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 6 +++--- lib/Target/PowerPC/PPCAsmPrinter.cpp | 17 ++++++++++++++++ lib/Target/PowerPC/PPCCodeEmitter.cpp | 6 +++--- lib/Target/PowerPC/PPCFrameLowering.cpp | 4 ++-- lib/Target/PowerPC/PPCInstr64Bit.td | 6 +++++- lib/Target/PowerPC/PPCInstrInfo.td | 8 +++++++- lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 +- test/CodeGen/PowerPC/crsave.ll | 20 +++++++++---------- test/MC/PowerPC/ppc64-encoding-ext.s | 2 ++ test/MC/PowerPC/ppc64-encoding.s | 8 ++++---- 10 files changed, 54 insertions(+), 25 deletions(-) diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index cb7f08b044c..27ad980703a 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -228,7 +228,7 @@ unsigned PPCMCCodeEmitter:: get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups) const { const MCOperand &MO = MI.getOperand(OpNo); - assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MTCRF8 || + assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 || MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); @@ -239,9 +239,9 @@ unsigned PPCMCCodeEmitter:: getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl &Fixups) const { if (MO.isReg()) { - // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. + // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. // The GPR operand should come through here though. - assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MTCRF8 && + assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 && MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) || MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp index 5129287e17c..8f41b2e7f74 100644 --- a/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -676,6 +676,23 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } break; + case PPC::MTOCRF: + case PPC::MTOCRF8: + if (!Subtarget.hasMFOCRF()) { + // Transform: %CR7 = MTOCRF %R3 + // Into: MTCRF mask, %R3 ;; cr7 + unsigned NewOpcode = + MI->getOpcode() == PPC::MTOCRF ? PPC::MTCRF : PPC::MTCRF8; + unsigned Mask = 0x80 >> OutContext.getRegisterInfo() + ->getEncodingValue(MI->getOperand(0).getReg()); + OutStreamer.AddComment(PPCInstPrinter:: + getRegisterName(MI->getOperand(0).getReg())); + OutStreamer.EmitInstruction(MCInstBuilder(NewOpcode) + .addImm(Mask) + .addReg(MI->getOperand(1).getReg())); + return; + } + break; case PPC::SYNC: // In Book E sync is called msync, handle this special case here... if (Subtarget.isBookE()) { diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index e9aa4c07ad7..418736e21e8 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -142,7 +142,7 @@ void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { unsigned PPCCodeEmitter::get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const { const MachineOperand &MO = MI.getOperand(OpNo); - assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MTCRF8 || + assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 || MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); return 0x80 >> TM.getRegisterInfo()->getEncodingValue(MO.getReg()); @@ -274,9 +274,9 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO) const { if (MO.isReg()) { - // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. + // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. // The GPR operand should come through here though. - assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MTCRF8 && + assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 && MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) || MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); return TM.getRegisterInfo()->getEncodingValue(MO.getReg()); diff --git a/lib/Target/PowerPC/PPCFrameLowering.cpp b/lib/Target/PowerPC/PPCFrameLowering.cpp index 4c57cf632fb..a19ce239377 100644 --- a/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -753,7 +753,7 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF, if (!MustSaveCRs.empty()) for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) - BuildMI(MBB, MBBI, dl, TII.get(PPC::MTCRF8), MustSaveCRs[i]) + BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) .addReg(PPC::X12, getKillRegState(i == e-1)); if (MustSaveLR) @@ -1212,7 +1212,7 @@ restoreCRs(bool isPPC64, bool is31, MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), PPC::R12), CSI[CSIIndex].getFrameIdx())); - RestoreOp = PPC::MTCRF; + RestoreOp = PPC::MTOCRF; MoveReg = PPC::R12; } diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 2426dcda1a6..d19a7d439fd 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -257,7 +257,11 @@ def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), // 64-bit CR instructions let Interpretation64Bit = 1 in { let neverHasSideEffects = 1 in { -def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins g8rc:$rS), +def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), + "mtocrf $FXM, $ST", BrMCRX>, + PPC970_DGroup_First, PPC970_Unit_CRU; + +def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), "mtcrf $FXM, $rS", BrMCRX>, PPC970_MicroCode, PPC970_Unit_CRU; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index e52adeeb29d..9a8e33b79d5 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -1898,7 +1898,11 @@ def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F), "#RESTORE_VRSAVE", []>; let neverHasSideEffects = 1 in { -def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins gprc:$rS), +def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), + "mtocrf $FXM, $ST", BrMCRX>, + PPC970_DGroup_First, PPC970_Unit_CRU; + +def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), "mtcrf $FXM, $rS", BrMCRX>, PPC970_MicroCode, PPC970_Unit_CRU; @@ -2322,6 +2326,8 @@ def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>; def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>; def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>; +def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>; + def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>; def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index e5b43051b71..8a0954c5bb5 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -403,7 +403,7 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, .addImm(31); } - BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg) + BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) .addReg(Reg, RegState::Kill); // Discard the pseudo instruction. diff --git a/test/CodeGen/PowerPC/crsave.ll b/test/CodeGen/PowerPC/crsave.ll index b15011d9284..a9b4b360783 100644 --- a/test/CodeGen/PowerPC/crsave.ll +++ b/test/CodeGen/PowerPC/crsave.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32 -; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64 +; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC32 +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC64 declare void @foo() @@ -18,7 +18,7 @@ entry: ; PPC32: mfcr 12 ; PPC32-NEXT: stw 12, 24(31) ; PPC32: lwz 12, 24(31) -; PPC32-NEXT: mtcrf 32, 12 +; PPC32-NEXT: mtocrf 32, 12 ; PPC64: .cfi_startproc ; PPC64: mfcr 12 @@ -29,7 +29,7 @@ entry: ; PPC64: .cfi_offset cr2, 8 ; PPC64: addi 1, 1, [[AMT]] ; PPC64: lwz 12, 8(1) -; PPC64: mtcrf 32, 12 +; PPC64: mtocrf 32, 12 ; PPC64: .cfi_endproc define i32 @test_cr234() nounwind { @@ -47,16 +47,16 @@ entry: ; PPC32: mfcr 12 ; PPC32-NEXT: stw 12, 24(31) ; PPC32: lwz 12, 24(31) -; PPC32-NEXT: mtcrf 32, 12 -; PPC32-NEXT: mtcrf 16, 12 -; PPC32-NEXT: mtcrf 8, 12 +; PPC32-NEXT: mtocrf 32, 12 +; PPC32-NEXT: mtocrf 16, 12 +; PPC32-NEXT: mtocrf 8, 12 ; PPC64: mfcr 12 ; PPC64: stw 12, 8(1) ; PPC64: stdu 1, -[[AMT:[0-9]+]](1) ; PPC64: addi 1, 1, [[AMT]] ; PPC64: lwz 12, 8(1) -; PPC64: mtcrf 32, 12 -; PPC64: mtcrf 16, 12 -; PPC64: mtcrf 8, 12 +; PPC64: mtocrf 32, 12 +; PPC64: mtocrf 16, 12 +; PPC64: mtocrf 8, 12 diff --git a/test/MC/PowerPC/ppc64-encoding-ext.s b/test/MC/PowerPC/ppc64-encoding-ext.s index 79c8fdb3921..0bc1a398355 100644 --- a/test/MC/PowerPC/ppc64-encoding-ext.s +++ b/test/MC/PowerPC/ppc64-encoding-ext.s @@ -1986,4 +1986,6 @@ not 2, 3 # CHECK: nor. 2, 3, 3 # encoding: [0x7c,0x62,0x18,0xf9] not. 2, 3 +# CHECK: mtcrf 255, 2 # encoding: [0x7c,0x4f,0xf1,0x20] + mtcr 2 diff --git a/test/MC/PowerPC/ppc64-encoding.s b/test/MC/PowerPC/ppc64-encoding.s index fbedf43d480..03d513ccc4d 100644 --- a/test/MC/PowerPC/ppc64-encoding.s +++ b/test/MC/PowerPC/ppc64-encoding.s @@ -508,12 +508,12 @@ mtspr 600, 2 # CHECK: mfspr 2, 600 # encoding: [0x7c,0x58,0x92,0xa6] mfspr 2, 600 -# CHECK: mtcrf 16, 2 # encoding: [0x7c,0x41,0x01,0x20] - mtcrf 16, 2 +# CHECK: mtcrf 123, 2 # encoding: [0x7c,0x47,0xb1,0x20] + mtcrf 123, 2 # CHECK: mfcr 2 # encoding: [0x7c,0x40,0x00,0x26] mfcr 2 -# FIXME: mtocrf 16, 2 +# CHECK: mtocrf 16, 2 # encoding: [0x7c,0x51,0x01,0x20] + mtocrf 16, 2 # CHECK: mfocrf 16, 8 # encoding: [0x7e,0x10,0x80,0x26] mfocrf 16, 8 -# FIXME: mcrxr 2