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R600/SI: Add more special cases for opcodes to ensureSRegLimit()
Also factor out the register class lookup to its own function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187830 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -673,43 +673,67 @@ bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
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return false;
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return false;
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}
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}
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const TargetRegisterClass *SITargetLowering::getRegClassForNode(
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SelectionDAG &DAG, const SDValue &Op) const {
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const SIInstrInfo *TII =
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static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
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const SIRegisterInfo &TRI = TII->getRegisterInfo();
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if (!Op->isMachineOpcode()) {
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switch(Op->getOpcode()) {
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case ISD::CopyFromReg: {
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MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
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unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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return MRI.getRegClass(Reg);
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}
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return TRI.getPhysRegClass(Reg);
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}
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default: return NULL;
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}
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}
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const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
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int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
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if (OpClassID != -1) {
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return TRI.getRegClass(OpClassID);
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}
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switch(Op.getMachineOpcode()) {
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case AMDGPU::COPY_TO_REGCLASS:
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// Operand 1 is the register class id for COPY_TO_REGCLASS instructions.
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OpClassID = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
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// If the COPY_TO_REGCLASS instruction is copying to a VSrc register
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// class, then the register class for the value could be either a
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// VReg or and SReg. In order to get a more accurate
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if (OpClassID == AMDGPU::VSrc_32RegClassID ||
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OpClassID == AMDGPU::VSrc_64RegClassID) {
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return getRegClassForNode(DAG, Op.getOperand(0));
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}
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return TRI.getRegClass(OpClassID);
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case AMDGPU::EXTRACT_SUBREG: {
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int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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const TargetRegisterClass *SuperClass =
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getRegClassForNode(DAG, Op.getOperand(0));
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return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
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}
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case AMDGPU::REG_SEQUENCE:
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// Operand 0 is the register class id for REG_SEQUENCE instructions.
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return TRI.getRegClass(
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cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue());
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default:
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return getRegClassFor(Op.getSimpleValueType());
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}
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}
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/// \brief Does "Op" fit into register class "RegClass" ?
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/// \brief Does "Op" fit into register class "RegClass" ?
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bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
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bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
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unsigned RegClass) const {
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unsigned RegClass) const {
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MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
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SDNode *Node = Op.getNode();
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const TargetRegisterClass *OpClass;
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const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
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const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
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if (MachineSDNode *MN = dyn_cast<MachineSDNode>(Node)) {
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const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
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const SIInstrInfo *TII =
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if (!RC) {
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static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
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const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode());
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int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
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if (OpClassID == -1) {
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switch (MN->getMachineOpcode()) {
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case AMDGPU::REG_SEQUENCE:
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// Operand 0 is the register class id for REG_SEQUENCE instructions.
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OpClass = TRI->getRegClass(
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cast<ConstantSDNode>(MN->getOperand(0))->getZExtValue());
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break;
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default:
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OpClass = getRegClassFor(Op.getSimpleValueType());
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break;
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}
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} else {
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OpClass = TRI->getRegClass(OpClassID);
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}
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} else if (Node->getOpcode() == ISD::CopyFromReg) {
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RegisterSDNode *Reg = cast<RegisterSDNode>(Node->getOperand(1).getNode());
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OpClass = MRI.getRegClass(Reg->getReg());
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} else
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return false;
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return false;
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}
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return TRI->getRegClass(RegClass)->hasSubClassEq(OpClass);
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return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
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}
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}
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/// \brief Make sure that we don't exeed the number of allowed scalars
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/// \brief Make sure that we don't exeed the number of allowed scalars
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@ -30,6 +30,8 @@ class SITargetLowering : public AMDGPUTargetLowering {
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bool foldImm(SDValue &Operand, int32_t &Immediate,
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bool foldImm(SDValue &Operand, int32_t &Immediate,
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bool &ScalarSlotUsed) const;
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bool &ScalarSlotUsed) const;
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const TargetRegisterClass *getRegClassForNode(SelectionDAG &DAG,
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const SDValue &Op) const;
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bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
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bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
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unsigned RegClass) const;
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unsigned RegClass) const;
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void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
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void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
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@ -49,3 +49,24 @@ const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
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case MVT::i32: return &AMDGPU::VReg_32RegClass;
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case MVT::i32: return &AMDGPU::VReg_32RegClass;
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}
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}
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}
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}
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const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
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assert(!TargetRegisterInfo::isVirtualRegister(Reg));
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const TargetRegisterClass *BaseClasses[] = {
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&AMDGPU::VReg_32RegClass,
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&AMDGPU::SReg_32RegClass,
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&AMDGPU::VReg_64RegClass,
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&AMDGPU::SReg_64RegClass,
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&AMDGPU::SReg_128RegClass,
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&AMDGPU::SReg_256RegClass
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};
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for (unsigned i = 0, e = sizeof(BaseClasses) /
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sizeof(const TargetRegisterClass*); i != e; ++i) {
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if (BaseClasses[i]->contains(Reg)) {
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return BaseClasses[i];
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}
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}
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return NULL;
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}
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@ -41,6 +41,10 @@ struct SIRegisterInfo : public AMDGPURegisterInfo {
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/// \brief get the register class of the specified type to use in the
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/// \brief get the register class of the specified type to use in the
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/// CFGStructurizer
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/// CFGStructurizer
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virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
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virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
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/// \brief Return the 'base' register class for this register.
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/// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc.
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const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
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};
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};
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} // End namespace llvm
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} // End namespace llvm
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@ -38,7 +38,7 @@ entry:
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; R600-CHECK: @bfi_sha256_ma
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; R600-CHECK: @bfi_sha256_ma
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; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W
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; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], KC0[2].Z, KC0[2].W
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; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W
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; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, KC0[3].X, KC0[2].W
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; SI-CHECK: V_XOR_B32_e64 [[DST:VGPR[0-9]+]], {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}
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; SI-CHECK: V_XOR_B32_e64 [[DST:VGPR[0-9]+]], {{[SV]GPR[0-9]+, VGPR[0-9]+}}
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; SI-CHECK: V_BFI_B32 {{VGPR[0-9]+}}, [[DST]], {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}
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; SI-CHECK: V_BFI_B32 {{VGPR[0-9]+}}, [[DST]], {{[SV]GPR[0-9]+, [SV]GPR[0-9]+}}
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define void @bfi_sha256_ma(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
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define void @bfi_sha256_ma(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
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@ -1,15 +1,15 @@
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15, 0, 0, -1
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;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15, 0, 0, -1
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;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 3, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 3, 0, 0, 0
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;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 2, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 2, 0, 0, 0
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;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 1, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 1, 0, 0, 0
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;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 4, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 4, 0, 0, 0
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;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 8, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 8, 0, 0, 0
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;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 5, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 5, 0, 0, 0
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;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 12, 0, 0, -1
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;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+}}, 12, 0, 0, -1
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;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7, 0, 0, 0
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;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7, 0, 0, 0
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;CHECK: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 8, 0, 0, -1
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;CHECK-DAG: IMAGE_LOAD_MIP {{VGPR[0-9]+}}, 8, 0, 0, -1
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define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
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define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
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%v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
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%v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
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@ -1,21 +1,21 @@
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15
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;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 3
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;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 3
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 2
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;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+}}, 2
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 1
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;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+}}, 1
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 4
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;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+}}, 4
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8
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;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 5
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;CHECK-DAG: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 5
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 9
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;CHECK-DAG: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 9
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 6
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;CHECK-DAG: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 6
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 10
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;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 10
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 12
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;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 12
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7
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;CHECK-DAG: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 11
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;CHECK-DAG: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 11
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;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 13
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;CHECK-DAG: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 13
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 14
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;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 14
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;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8
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;CHECK-DAG: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8
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define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
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define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
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%v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
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%v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
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@ -1,21 +1,21 @@
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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;CHECK: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15
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;CHECK: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 3
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 3
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;CHECK: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 2
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 2
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;CHECK: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 1
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 1
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;CHECK: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 4
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 4
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;CHECK: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 8
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 8
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;CHECK: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+}}, 5
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;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+}}, 5
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;CHECK: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+}}, 9
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;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+}}, 9
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;CHECK: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+}}, 6
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;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+}}, 6
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;CHECK: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 10
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 10
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;CHECK: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 12
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;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+}}, 12
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;CHECK: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7
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;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7
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;CHECK: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 11
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;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 11
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;CHECK: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 13
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;CHECK-DAG: IMAGE_SAMPLE_C_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 13
|
||||||
;CHECK: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 14
|
;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 14
|
||||||
;CHECK: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 8
|
;CHECK-DAG: IMAGE_SAMPLE_D {{VGPR[0-9]+}}, 8
|
||||||
|
|
||||||
define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
|
define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
|
||||||
%v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
|
%v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
|
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
|
||||||
|
|
||||||
;CHECK: V_LSHL_B32_e64 VGPR{{[0-9]+}}, {{[SV]GPR[0-9]+}}, 1
|
;CHECK: V_LSHL_B32_e64 VGPR{{[0-9]}}, SGPR{{[0-9]}}, 1
|
||||||
|
|
||||||
define void @test(i32 %p) {
|
define void @test(i32 %p) {
|
||||||
%i = mul i32 %p, 2
|
%i = mul i32 %p, 2
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
|
;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
|
||||||
|
|
||||||
;CHECK: V_LSHR_B32_e64 {{VGPR[0-9]+}}, {{[SV]GPR[0-9]+}}, 1
|
;CHECK: V_LSHR_B32_e64 {{VGPR[0-9]}}, SGPR{{[0-9]}}, 1
|
||||||
|
|
||||||
define void @test(i32 %p) {
|
define void @test(i32 %p) {
|
||||||
%i = udiv i32 %p, 2
|
%i = udiv i32 %p, 2
|
||||||
|
Loading…
Reference in New Issue
Block a user