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Switch to generating machineinstr's instead of MInstructions

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4396 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2002-10-29 17:43:55 +00:00
parent a535fabe7d
commit 341a937169
2 changed files with 38 additions and 38 deletions
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38
lib/Target/X86/InstSelectSimple.cpp
View File

@@ -10,20 +10,20 @@
#include "llvm/iTerminators.h" #include "llvm/iTerminators.h"
#include "llvm/Type.h" #include "llvm/Type.h"
#include "llvm/Constants.h" #include "llvm/Constants.h"
#include "llvm/CodeGen/MFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MInstBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Support/InstVisitor.h" #include "llvm/Support/InstVisitor.h"
#include <map> #include <map>
namespace { namespace {
struct ISel : public InstVisitor<ISel> { // eventually will be a FunctionPass struct ISel : public InstVisitor<ISel> { // eventually will be a FunctionPass
MFunction *F; // The function we are compiling into MachineFunction *F; // The function we are compiling into
MBasicBlock *BB; // The current basic block we are compiling MachineBasicBlock *BB; // The current MBB we are compiling
unsigned CurReg; unsigned CurReg;
std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
ISel(MFunction *f) ISel(MachineFunction *f)
: F(f), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {} : F(f), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
/// runOnFunction - Top level implementation of instruction selection for /// runOnFunction - Top level implementation of instruction selection for
@@ -41,7 +41,7 @@ namespace {
/// invoked for all instructions in the basic block. /// invoked for all instructions in the basic block.
/// ///
void visitBasicBlock(BasicBlock &LLVM_BB) { void visitBasicBlock(BasicBlock &LLVM_BB) {
BB = new MBasicBlock(); BB = new MachineBasicBlock();
// FIXME: Use the auto-insert form when it's available // FIXME: Use the auto-insert form when it's available
F->getBasicBlockList().push_back(BB); F->getBasicBlockList().push_back(BB);
} }
@@ -94,22 +94,22 @@ void ISel::copyConstantToRegister(Constant *C, unsigned R) {
switch (C->getType()->getPrimitiveID()) { switch (C->getType()->getPrimitiveID()) {
case Type::SByteTyID: case Type::SByteTyID:
BuildMInst(BB, X86::MOVir8, R).addSImm(cast<ConstantSInt>(C)->getValue()); BuildMI(BB, X86::MOVir8, R).addSImm(cast<ConstantSInt>(C)->getValue());
break; break;
case Type::UByteTyID: case Type::UByteTyID:
BuildMInst(BB, X86::MOVir8, R).addZImm(cast<ConstantUInt>(C)->getValue()); BuildMI(BB, X86::MOVir8, R).addZImm(cast<ConstantUInt>(C)->getValue());
break; break;
case Type::ShortTyID: case Type::ShortTyID:
BuildMInst(BB, X86::MOVir16, R).addSImm(cast<ConstantSInt>(C)->getValue()); BuildMI(BB, X86::MOVir16, R).addSImm(cast<ConstantSInt>(C)->getValue());
break; break;
case Type::UShortTyID: case Type::UShortTyID:
BuildMInst(BB, X86::MOVir16, R).addZImm(cast<ConstantUInt>(C)->getValue()); BuildMI(BB, X86::MOVir16, R).addZImm(cast<ConstantUInt>(C)->getValue());
break; break;
case Type::IntTyID: case Type::IntTyID:
BuildMInst(BB, X86::MOVir32, R).addSImm(cast<ConstantSInt>(C)->getValue()); BuildMI(BB, X86::MOVir32, R).addSImm(cast<ConstantSInt>(C)->getValue());
break; break;
case Type::UIntTyID: case Type::UIntTyID:
BuildMInst(BB, X86::MOVir32, R).addZImm(cast<ConstantUInt>(C)->getValue()); BuildMI(BB, X86::MOVir32, R).addZImm(cast<ConstantUInt>(C)->getValue());
break; break;
default: assert(0 && "Type not handled yet!"); default: assert(0 && "Type not handled yet!");
} }
@@ -135,7 +135,7 @@ void ISel::visitReturnInst(ReturnInst &I) {
// Emit a simple 'ret' instruction... appending it to the end of the basic // Emit a simple 'ret' instruction... appending it to the end of the basic
// block // block
new MInstruction(BB, X86::RET); BuildMI(BB, X86::RET, 0);
} }
@@ -146,13 +146,13 @@ void ISel::visitAdd(BinaryOperator &B) {
switch (B.getType()->getPrimitiveSize()) { switch (B.getType()->getPrimitiveSize()) {
case 1: // UByte, SByte case 1: // UByte, SByte
BuildMInst(BB, X86::ADDrr8, DestReg).addReg(Op0r).addReg(Op1r); BuildMI(BB, X86::ADDrr8, DestReg).addReg(Op0r).addReg(Op1r);
break; break;
case 2: // UShort, Short case 2: // UShort, Short
BuildMInst(BB, X86::ADDrr16, DestReg).addReg(Op0r).addReg(Op1r); BuildMI(BB, X86::ADDrr16, DestReg).addReg(Op0r).addReg(Op1r);
break; break;
case 4: // UInt, Int case 4: // UInt, Int
BuildMInst(BB, X86::ADDrr32, DestReg).addReg(Op0r).addReg(Op1r); BuildMI(BB, X86::ADDrr32, DestReg).addReg(Op0r).addReg(Op1r);
break; break;
case 8: // ULong, Long case 8: // ULong, Long
@@ -167,8 +167,8 @@ void ISel::visitAdd(BinaryOperator &B) {
/// a machine code representation is a very simple peep-hole fashion. The /// a machine code representation is a very simple peep-hole fashion. The
/// generated code sucks but the implementation is nice and simple. /// generated code sucks but the implementation is nice and simple.
/// ///
MFunction *X86SimpleInstructionSelection(Function &F) { MachineFunction *X86SimpleInstructionSelection(Function &F, TargetMachine &TM) {
MFunction *Result = new MFunction(); MachineFunction *Result = new MachineFunction(&F, TM);
ISel(Result).runOnFunction(F); ISel(Result).runOnFunction(F);
return Result; return Result;
} }

38
lib/Target/X86/X86ISelSimple.cpp
View File

@@ -10,20 +10,20 @@
#include "llvm/iTerminators.h" #include "llvm/iTerminators.h"
#include "llvm/Type.h" #include "llvm/Type.h"
#include "llvm/Constants.h" #include "llvm/Constants.h"
#include "llvm/CodeGen/MFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MInstBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Support/InstVisitor.h" #include "llvm/Support/InstVisitor.h"
#include <map> #include <map>
namespace { namespace {
struct ISel : public InstVisitor<ISel> { // eventually will be a FunctionPass struct ISel : public InstVisitor<ISel> { // eventually will be a FunctionPass
MFunction *F; // The function we are compiling into MachineFunction *F; // The function we are compiling into
MBasicBlock *BB; // The current basic block we are compiling MachineBasicBlock *BB; // The current MBB we are compiling
unsigned CurReg; unsigned CurReg;
std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
ISel(MFunction *f) ISel(MachineFunction *f)
: F(f), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {} : F(f), BB(0), CurReg(MRegisterInfo::FirstVirtualRegister) {}
/// runOnFunction - Top level implementation of instruction selection for /// runOnFunction - Top level implementation of instruction selection for
@@ -41,7 +41,7 @@ namespace {
/// invoked for all instructions in the basic block. /// invoked for all instructions in the basic block.
/// ///
void visitBasicBlock(BasicBlock &LLVM_BB) { void visitBasicBlock(BasicBlock &LLVM_BB) {
BB = new MBasicBlock(); BB = new MachineBasicBlock();
// FIXME: Use the auto-insert form when it's available // FIXME: Use the auto-insert form when it's available
F->getBasicBlockList().push_back(BB); F->getBasicBlockList().push_back(BB);
} }
@@ -94,22 +94,22 @@ void ISel::copyConstantToRegister(Constant *C, unsigned R) {
switch (C->getType()->getPrimitiveID()) { switch (C->getType()->getPrimitiveID()) {
case Type::SByteTyID: case Type::SByteTyID:
BuildMInst(BB, X86::MOVir8, R).addSImm(cast<ConstantSInt>(C)->getValue()); BuildMI(BB, X86::MOVir8, R).addSImm(cast<ConstantSInt>(C)->getValue());
break; break;
case Type::UByteTyID: case Type::UByteTyID:
BuildMInst(BB, X86::MOVir8, R).addZImm(cast<ConstantUInt>(C)->getValue()); BuildMI(BB, X86::MOVir8, R).addZImm(cast<ConstantUInt>(C)->getValue());
break; break;
case Type::ShortTyID: case Type::ShortTyID:
BuildMInst(BB, X86::MOVir16, R).addSImm(cast<ConstantSInt>(C)->getValue()); BuildMI(BB, X86::MOVir16, R).addSImm(cast<ConstantSInt>(C)->getValue());
break; break;
case Type::UShortTyID: case Type::UShortTyID:
BuildMInst(BB, X86::MOVir16, R).addZImm(cast<ConstantUInt>(C)->getValue()); BuildMI(BB, X86::MOVir16, R).addZImm(cast<ConstantUInt>(C)->getValue());
break; break;
case Type::IntTyID: case Type::IntTyID:
BuildMInst(BB, X86::MOVir32, R).addSImm(cast<ConstantSInt>(C)->getValue()); BuildMI(BB, X86::MOVir32, R).addSImm(cast<ConstantSInt>(C)->getValue());
break; break;
case Type::UIntTyID: case Type::UIntTyID:
BuildMInst(BB, X86::MOVir32, R).addZImm(cast<ConstantUInt>(C)->getValue()); BuildMI(BB, X86::MOVir32, R).addZImm(cast<ConstantUInt>(C)->getValue());
break; break;
default: assert(0 && "Type not handled yet!"); default: assert(0 && "Type not handled yet!");
} }
@@ -135,7 +135,7 @@ void ISel::visitReturnInst(ReturnInst &I) {
// Emit a simple 'ret' instruction... appending it to the end of the basic // Emit a simple 'ret' instruction... appending it to the end of the basic
// block // block
new MInstruction(BB, X86::RET); BuildMI(BB, X86::RET, 0);
} }
@@ -146,13 +146,13 @@ void ISel::visitAdd(BinaryOperator &B) {
switch (B.getType()->getPrimitiveSize()) { switch (B.getType()->getPrimitiveSize()) {
case 1: // UByte, SByte case 1: // UByte, SByte
BuildMInst(BB, X86::ADDrr8, DestReg).addReg(Op0r).addReg(Op1r); BuildMI(BB, X86::ADDrr8, DestReg).addReg(Op0r).addReg(Op1r);
break; break;
case 2: // UShort, Short case 2: // UShort, Short
BuildMInst(BB, X86::ADDrr16, DestReg).addReg(Op0r).addReg(Op1r); BuildMI(BB, X86::ADDrr16, DestReg).addReg(Op0r).addReg(Op1r);
break; break;
case 4: // UInt, Int case 4: // UInt, Int
BuildMInst(BB, X86::ADDrr32, DestReg).addReg(Op0r).addReg(Op1r); BuildMI(BB, X86::ADDrr32, DestReg).addReg(Op0r).addReg(Op1r);
break; break;
case 8: // ULong, Long case 8: // ULong, Long
@@ -167,8 +167,8 @@ void ISel::visitAdd(BinaryOperator &B) {
/// a machine code representation is a very simple peep-hole fashion. The /// a machine code representation is a very simple peep-hole fashion. The
/// generated code sucks but the implementation is nice and simple. /// generated code sucks but the implementation is nice and simple.
/// ///
MFunction *X86SimpleInstructionSelection(Function &F) { MachineFunction *X86SimpleInstructionSelection(Function &F, TargetMachine &TM) {
MFunction *Result = new MFunction(); MachineFunction *Result = new MachineFunction(&F, TM);
ISel(Result).runOnFunction(F); ISel(Result).runOnFunction(F);
return Result; return Result;
} }