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Actually fix PPC64 64-bit GPR inline asm constraint matching

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This is a follow-up to r187693, correcting that code to request the correct
register class. The previous version, with the wrong register class, was not
really correcting the constraints, but rather was removing them. Coincidentally,
this fixed the failing test case in r187693, but obviously created other
problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188407 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-08-14 20:05:04 +00:00
parent fdb1a6c341
commit 341c1a50ad
2 changed files with 44 additions and 1 deletions
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2
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -7591,7 +7591,7 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
PPC::GPRCRegClass.contains(R.first)) { PPC::GPRCRegClass.contains(R.first)) {
const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
return std::make_pair(TRI->getMatchingSuperReg(R.first, return std::make_pair(TRI->getMatchingSuperReg(R.first,
PPC::sub_32, &PPC::GPRCRegClass), PPC::sub_32, &PPC::G8RCRegClass),
&PPC::G8RCRegClass); &PPC::G8RCRegClass);
} }

43
test/CodeGen/PowerPC/inlineasm-i64-reg.ll
View File

@ -59,6 +59,49 @@ entry:
ret i32 %conv ret i32 %conv
} }
declare void @mtrace()
define signext i32 @main(i32 signext %argc, i8** %argv) {
entry:
%argc.addr = alloca i32, align 4
store i32 %argc, i32* %argc.addr, align 4
%0 = call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1076)
%asmresult1.i = extractvalue { i64, i64 } %0, 1
%conv.i = trunc i64 %asmresult1.i to i32
%cmp = icmp eq i32 %conv.i, 0
br i1 %cmp, label %if.then, label %if.end
; CHECK-LABEL: @main
; CHECK-DAG: mr [[REG:[0-9]+]], 3
; CHECK-DAG: li 0, 1076
; CHECK: stw [[REG]],
; CHECK: #APP
; CHECK: sc
; CHECK: #NO_APP
; CHECK: cmpwi {{[0-9]+}}, [[REG]], 1
; CHECK: blr
if.then: ; preds = %entry
call void @mtrace()
%.pre = load i32* %argc.addr, align 4
br label %if.end
if.end: ; preds = %if.then, %entry
%1 = phi i32 [ %.pre, %if.then ], [ %argc, %entry ]
%cmp1 = icmp slt i32 %1, 2
br i1 %cmp1, label %usage, label %if.end40
usage:
ret i32 8
if.end40:
ret i32 0
}
attributes #0 = { alwaysinline inlinehint nounwind } attributes #0 = { alwaysinline inlinehint nounwind }
attributes #1 = { nounwind } attributes #1 = { nounwind }