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https://github.com/c64scene-ar/llvm-6502.git
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[X86] Declare SSE4.1/AVX2 vector extloads covered by PMOV[SZ]X legal.
Now that we can fully specify extload legality, we can declare them legal for the PMOVSX/PMOVZX instructions. This for instance enables a DAGCombine to fire on code such as (and (<zextload-equivalent> ...), <redundant mask>) to turn it into: (zextload ...) as seen in the testcase changes. There is one regression, in widen_load-2.ll: we're no longer able to do store-to-load forwarding with illegal extload memory types. This will be addressed separately. Differential Revision: http://reviews.llvm.org/D6533 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226676 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha
parent
b727b13f61
commit
34288d885e
@ -1136,6 +1136,21 @@ void X86TargetLowering::resetOperationActions() {
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
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}
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// SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
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setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
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// i8 and i16 vectors are custom because the source register and source
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// source memory operand types are not the same width. f32 vectors are
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// custom since the immediate controlling the insert encodes additional
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@ -1315,6 +1330,21 @@ void X86TargetLowering::resetOperationActions() {
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// Custom CTPOP always performs better on natively supported v8i32
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setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
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// AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
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setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
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} else {
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setOperationAction(ISD::ADD, MVT::v4i64, Custom);
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setOperationAction(ISD::ADD, MVT::v8i32, Custom);
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@ -6120,7 +6120,7 @@ defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
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defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
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// AVX2 Patterns
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multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, SDNode ExtOp> {
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multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
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// Register-Register patterns
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def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
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(!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
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@ -6154,6 +6154,22 @@ multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, SDNode ExtOp> {
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def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
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(!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
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// Simple Register-Memory patterns
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def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
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(!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
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def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
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(!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
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def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
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(!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
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def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
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(!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
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def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
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(!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
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def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
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(!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
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// AVX2 Register-Memory patterns
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def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
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(!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
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@ -6211,13 +6227,13 @@ multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, SDNode ExtOp> {
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}
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let Predicates = [HasAVX2] in {
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defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", X86vsext>;
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defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", X86vzext>;
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defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
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defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
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}
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// SSE4.1/AVX patterns.
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multiclass SS41I_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
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PatFrag ExtLoad16> {
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multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
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SDNode ExtOp, PatFrag ExtLoad16> {
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def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
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(!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
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def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
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@ -6233,6 +6249,21 @@ multiclass SS41I_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
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def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
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(!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
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def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
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(!cast<I>(OpcPrefix#BWrm) addr:$src)>;
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def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
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(!cast<I>(OpcPrefix#BDrm) addr:$src)>;
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def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
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(!cast<I>(OpcPrefix#BQrm) addr:$src)>;
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def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
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(!cast<I>(OpcPrefix#WDrm) addr:$src)>;
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def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
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(!cast<I>(OpcPrefix#WQrm) addr:$src)>;
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def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
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(!cast<I>(OpcPrefix#DQrm) addr:$src)>;
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def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
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(!cast<I>(OpcPrefix#BWrm) addr:$src)>;
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def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
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@ -6295,13 +6326,13 @@ multiclass SS41I_pmovx_patterns<string OpcPrefix, SDNode ExtOp,
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}
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let Predicates = [HasAVX] in {
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defm : SS41I_pmovx_patterns<"VPMOVSX", X86vsext, extloadi32i16>;
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defm : SS41I_pmovx_patterns<"VPMOVZX", X86vzext, loadi16_anyext>;
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defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
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defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
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}
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let Predicates = [UseSSE41] in {
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defm : SS41I_pmovx_patterns<"PMOVSX", X86vsext, extloadi32i16>;
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defm : SS41I_pmovx_patterns<"PMOVZX", X86vzext, loadi16_anyext>;
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defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
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defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
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}
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//===----------------------------------------------------------------------===//
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@ -15,8 +15,6 @@ define void @test_avx2_pmovx_256(<8 x i8>* %tmp64, <8 x float>* %tmp75) {
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; CHECK-LABEL: test_avx2_pmovx_256
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; We really don't care about the generated code.
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; CHECK: vpmovzxbd
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; CHECK: vpbroadcastd
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; CHECK: vpand
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; CHECK: vcvtdq2ps
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; CHECK: vmovups
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; CHECK: vzeroupper
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@ -81,8 +81,7 @@ define <4 x i32*> @INT2PTR1(<4 x i8>* %p) nounwind {
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entry:
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%G = load <4 x i8>* %p
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;CHECK: movl
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;CHECK: pmovzxbd
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;CHECK: pand
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;CHECK: pmovzxbd (%
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%K = inttoptr <4 x i8> %G to <4 x i32*>
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;CHECK: ret
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ret <4 x i32*> %K
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@ -191,8 +191,9 @@ define void @rot(%i8vec3pack* nocapture sret %result, %i8vec3pack* %X, %i8vec3pa
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; CHECK-NEXT: movd %[[CONSTANT1]], %e[[R1:[abcd]]]x
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; CHECK-NEXT: movw %[[R1]]x, (%[[PTR1:.*]])
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; CHECK-NEXT: movb $1, 2(%[[PTR1]])
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; CHECK-NEXT: pmovzxbd (%[[PTR0]]), %[[X0:xmm[0-9]+]]
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; CHECK-NEXT: pand {{.*}}, %[[X0]]
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; CHECK-NEXT: movl (%[[PTR0]]), [[TMP1:%e[abcd]+x]]
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; CHECK-NEXT: movl [[TMP1]], [[TMP2:.*]]
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; CHECK-NEXT: pmovzxbd [[TMP2]], %[[X0:xmm[0-9]+]]
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; CHECK-NEXT: pextrd $1, %[[X0]], %e[[R0:[abcd]]]x
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; CHECK-NEXT: shrl %e[[R0]]x
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; CHECK-NEXT: movd %[[X0]], %e[[R1:[abcd]]]x
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