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R600/SI: Remove explicit VOP operand checking
This should be handled by the OperandType checking. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229750 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1230,34 +1230,6 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
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}
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}
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}
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}
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// Verify SRC1 for VOP2 and VOPC
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if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
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const MachineOperand &Src1 = MI->getOperand(Src1Idx);
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if (Src1.isImm()) {
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ErrInfo = "VOP[2C] src1 cannot be an immediate.";
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return false;
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}
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}
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// Verify VOP3
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if (isVOP3(Opcode)) {
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if (Src0Idx != -1 &&
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isLiteralConstant(MI->getOperand(Src0Idx), getOpSize(Opcode, Src0Idx))) {
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ErrInfo = "VOP3 src0 cannot be a literal constant.";
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return false;
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}
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if (Src1Idx != -1 &&
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isLiteralConstant(MI->getOperand(Src1Idx), getOpSize(Opcode, Src1Idx))) {
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ErrInfo = "VOP3 src1 cannot be a literal constant.";
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return false;
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}
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if (Src2Idx != -1 &&
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isLiteralConstant(MI->getOperand(Src2Idx), getOpSize(Opcode, Src2Idx))) {
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ErrInfo = "VOP3 src2 cannot be a literal constant.";
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return false;
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}
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}
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// Verify misc. restrictions on specific instructions.
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// Verify misc. restrictions on specific instructions.
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if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
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if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
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Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
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Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
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