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Fix 80-columns

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139525 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2011-09-12 19:30:29 +00:00
parent a3157b4026
commit 3445df77d4
1 changed files with 16 additions and 12 deletions
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28
lib/Target/X86/X86InstrSSE.td
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@ -1999,21 +1999,25 @@ let neverHasSideEffects = 1 in {
let Constraints = "$src1 = $dst" in {
def CMPSSrr : SIi8<0xC2, MRMSrcReg,
(outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
"cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
[(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
(outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
"cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
[(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2,
imm:$cc))]>, XS;
def CMPSSrm : SIi8<0xC2, MRMSrcMem,
(outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
"cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
[(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
(outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
"cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
[(set FR32:$dst, (X86cmpss (f32 FR32:$src1),
(loadf32 addr:$src2), imm:$cc))]>, XS;
def CMPSDrr : SIi8<0xC2, MRMSrcReg,
(outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
"cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
[(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
(outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
"cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
[(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2,
imm:$cc))]>, XD;
def CMPSDrm : SIi8<0xC2, MRMSrcMem,
(outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
"cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
[(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
(outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
"cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
[(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2),
imm:$cc))]>, XD;
}
let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,