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Allow lr in the register options here.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133935 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2011-06-27 20:31:01 +00:00
parent 0d06bb9548
commit 34720e193f
1 changed files with 3 additions and 3 deletions
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6
test/CodeGen/ARM/arm-modifier.ll
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@ -46,9 +46,9 @@ ret void
define void @f3() nounwind {
entry:
; CHECK: f3
; CHECK: stm r{{[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}
; CHECK: adds lr, [[REG1]]
; CHECK: ldm r{{[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}}
; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}
; CHECK: adds {{lr|r[0-9]+}}, [[REG1]]
; CHECK: ldm {{lr|r[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}}
%tmp = load i64* @f3_var, align 4
%tmp1 = load i64* @f3_var2, align 4
%0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(i64** @f3_ptr, i64 %tmp, i64 %tmp1) nounwind