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Add aggressive anti-dependence breaker. Currently it is not the default for any target. Enable with -break-anti-dependencies=all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85145 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Goodwin
parent
6000e253d4
commit
348777110a
687
lib/CodeGen/AggressiveAntiDepBreaker.cpp
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687
lib/CodeGen/AggressiveAntiDepBreaker.cpp
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@ -0,0 +1,687 @@
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//===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AggressiveAntiDepBreaker class, which
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// implements register anti-dependence breaking during post-RA
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// scheduling. It attempts to break all anti-dependencies within a
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// block.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "aggressive-antidep"
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#include "AggressiveAntiDepBreaker.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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AggressiveAntiDepBreaker::
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AggressiveAntiDepBreaker(MachineFunction& MFi) :
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AntiDepBreaker(), MF(MFi),
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MRI(MF.getRegInfo()),
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TRI(MF.getTarget().getRegisterInfo()),
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AllocatableSet(TRI->getAllocatableSet(MF)),
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GroupNodes(TargetRegisterInfo::FirstVirtualRegister, 0)
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{
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}
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AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
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}
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void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
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// Initialize all registers to be in their own group. Initially we
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// assign the register to the same-indexed GroupNode.
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for (unsigned i = 0; i < TargetRegisterInfo::FirstVirtualRegister; ++i)
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GroupNodeIndices[i] = i;
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// Initialize the indices to indicate that no registers are live.
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std::fill(KillIndices, array_endof(KillIndices), ~0u);
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std::fill(DefIndices, array_endof(DefIndices), BB->size());
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bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
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// Determine the live-out physregs for this block.
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if (IsReturnBlock) {
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// In a return block, examine the function live-out regs.
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for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
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E = MRI.liveout_end(); I != E; ++I) {
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unsigned Reg = *I;
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UnionGroups(Reg, 0);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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UnionGroups(AliasReg, 0);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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}
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}
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} else {
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// In a non-return block, examine the live-in regs of all successors.
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for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
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SE = BB->succ_end(); SI != SE; ++SI)
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for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
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E = (*SI)->livein_end(); I != E; ++I) {
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unsigned Reg = *I;
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UnionGroups(Reg, 0);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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UnionGroups(AliasReg, 0);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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}
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}
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}
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// Mark live-out callee-saved registers. In a return block this is
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// all callee-saved registers. In non-return this is any
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// callee-saved register that is not saved in the prolog.
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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BitVector Pristine = MFI->getPristineRegs(BB);
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for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
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unsigned Reg = *I;
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if (!IsReturnBlock && !Pristine.test(Reg)) continue;
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UnionGroups(Reg, 0);
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KillIndices[Reg] = BB->size();
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DefIndices[Reg] = ~0u;
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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UnionGroups(AliasReg, 0);
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KillIndices[AliasReg] = BB->size();
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DefIndices[AliasReg] = ~0u;
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}
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}
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}
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void AggressiveAntiDepBreaker::FinishBlock() {
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RegRefs.clear();
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}
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void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
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unsigned InsertPosIndex) {
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assert(Count < InsertPosIndex && "Instruction index out of expected range!");
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DEBUG(errs() << "Observe: ");
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DEBUG(MI->dump());
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for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg) {
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// If Reg is current live, then mark that it can't be renamed as
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// we don't know the extent of its live-range anymore (now that it
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// has been scheduled). If it is not live but was defined in the
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// previous schedule region, then set its def index to the most
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// conservative location (i.e. the beginning of the previous
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// schedule region).
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if (IsLive(Reg)) {
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DEBUG(if (GetGroup(Reg) != 0)
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errs() << " " << TRI->getName(Reg) << "=g" <<
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GetGroup(Reg) << "->g0(region live-out)");
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UnionGroups(Reg, 0);
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} else if ((DefIndices[Reg] < InsertPosIndex) && (DefIndices[Reg] >= Count)) {
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DefIndices[Reg] = Count;
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}
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}
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std::set<unsigned> PassthruRegs;
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GetPassthruRegs(MI, PassthruRegs);
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PrescanInstruction(MI, Count, PassthruRegs);
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ScanInstruction(MI, Count);
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}
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unsigned AggressiveAntiDepBreaker::GetGroup(unsigned Reg)
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{
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unsigned Node = GroupNodeIndices[Reg];
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while (GroupNodes[Node] != Node)
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Node = GroupNodes[Node];
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return Node;
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}
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void AggressiveAntiDepBreaker::GetGroupRegs(unsigned Group, std::vector<unsigned> &Regs)
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{
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for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg) {
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if (GetGroup(Reg) == Group)
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Regs.push_back(Reg);
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}
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}
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unsigned AggressiveAntiDepBreaker::UnionGroups(unsigned Reg1, unsigned Reg2)
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{
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assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
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assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
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// find group for each register
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unsigned Group1 = GetGroup(Reg1);
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unsigned Group2 = GetGroup(Reg2);
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// if either group is 0, then that must become the parent
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unsigned Parent = (Group1 == 0) ? Group1 : Group2;
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unsigned Other = (Parent == Group1) ? Group2 : Group1;
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GroupNodes.at(Other) = Parent;
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return Parent;
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}
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unsigned AggressiveAntiDepBreaker::LeaveGroup(unsigned Reg)
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{
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// Create a new GroupNode for Reg. Reg's existing GroupNode must
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// stay as is because there could be other GroupNodes referring to
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// it.
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unsigned idx = GroupNodes.size();
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GroupNodes.push_back(idx);
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GroupNodeIndices[Reg] = idx;
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return idx;
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}
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bool AggressiveAntiDepBreaker::IsLive(unsigned Reg)
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{
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// KillIndex must be defined and DefIndex not defined for a register
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// to be live.
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return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
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}
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bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI,
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MachineOperand& MO)
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{
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if (!MO.isReg() || !MO.isImplicit())
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return false;
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unsigned Reg = MO.getReg();
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if (Reg == 0)
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return false;
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MachineOperand *Op = NULL;
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if (MO.isDef())
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Op = MI->findRegisterUseOperand(Reg, true);
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else
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Op = MI->findRegisterDefOperand(Reg);
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return((Op != NULL) && Op->isImplicit());
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}
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void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI,
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std::set<unsigned>& PassthruRegs) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
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IsImplicitDefUse(MI, MO)) {
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const unsigned Reg = MO.getReg();
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PassthruRegs.insert(Reg);
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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*Subreg; ++Subreg) {
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PassthruRegs.insert(*Subreg);
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}
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}
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}
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}
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/// AntiDepPathStep - Return SUnit that SU has an anti-dependence on.
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static void AntiDepPathStep(SUnit *SU, std::vector<SDep*>& Edges) {
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SmallSet<unsigned, 8> Dups;
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for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
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P != PE; ++P) {
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if (P->getKind() == SDep::Anti) {
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unsigned Reg = P->getReg();
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if (Dups.count(Reg) == 0) {
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Edges.push_back(&*P);
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Dups.insert(Reg);
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}
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}
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}
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}
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void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Count,
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std::set<unsigned>& PassthruRegs) {
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// Scan the register defs for this instruction and update
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// live-ranges, groups and RegRefs.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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// Ignore passthru registers for liveness...
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if (PassthruRegs.count(Reg) != 0) continue;
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// Update Def for Reg and subregs.
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DefIndices[Reg] = Count;
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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*Subreg; ++Subreg) {
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unsigned SubregReg = *Subreg;
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DefIndices[SubregReg] = Count;
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}
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}
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DEBUG(errs() << "\tDef Groups:");
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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DEBUG(errs() << " " << TRI->getName(Reg) << "=g" << GetGroup(Reg));
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// If MI's defs have special allocation requirement, don't allow
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// any def registers to be changed. Also assume all registers
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// defined in a call must not be changed (ABI).
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if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq()) {
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DEBUG(if (GetGroup(Reg) != 0) errs() << "->g0(alloc-req)");
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UnionGroups(Reg, 0);
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}
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// Any aliased that are live at this point are completely or
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// partially defined here, so group those subregisters with Reg.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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if (IsLive(AliasReg)) {
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UnionGroups(Reg, AliasReg);
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DEBUG(errs() << "->g" << GetGroup(Reg) << "(via " <<
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TRI->getName(AliasReg) << ")");
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}
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}
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// Note register reference...
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const TargetRegisterClass *RC = NULL;
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if (i < MI->getDesc().getNumOperands())
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RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
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RegisterReference RR = { &MO, RC };
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RegRefs.insert(std::make_pair(Reg, RR));
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}
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DEBUG(errs() << '\n');
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}
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void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
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unsigned Count) {
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DEBUG(errs() << "\tUse Groups:");
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// Scan the register uses for this instruction and update
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// live-ranges, groups and RegRefs.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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DEBUG(errs() << " " << TRI->getName(Reg) << "=g" << GetGroup(Reg));
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// It wasn't previously live but now it is, this is a kill. Forget
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// the previous live-range information and start a new live-range
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// for the register.
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if (!IsLive(Reg)) {
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KillIndices[Reg] = Count;
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DefIndices[Reg] = ~0u;
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RegRefs.erase(Reg);
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LeaveGroup(Reg);
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DEBUG(errs() << "->g" << GetGroup(Reg) << "(last-use)");
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}
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// Repeat, for subregisters.
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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*Subreg; ++Subreg) {
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unsigned SubregReg = *Subreg;
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if (!IsLive(SubregReg)) {
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KillIndices[SubregReg] = Count;
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DefIndices[SubregReg] = ~0u;
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RegRefs.erase(SubregReg);
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LeaveGroup(SubregReg);
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DEBUG(errs() << " " << TRI->getName(SubregReg) << "->g" <<
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GetGroup(SubregReg) << "(last-use)");
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}
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}
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// If MI's uses have special allocation requirement, don't allow
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// any use registers to be changed. Also assume all registers
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// used in a call must not be changed (ABI).
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if (MI->getDesc().isCall() || MI->getDesc().hasExtraSrcRegAllocReq()) {
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DEBUG(if (GetGroup(Reg) != 0) errs() << "->g0(alloc-req)");
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UnionGroups(Reg, 0);
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}
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// Note register reference...
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const TargetRegisterClass *RC = NULL;
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if (i < MI->getDesc().getNumOperands())
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RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
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RegisterReference RR = { &MO, RC };
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RegRefs.insert(std::make_pair(Reg, RR));
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}
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DEBUG(errs() << '\n');
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// Form a group of all defs and uses of a KILL instruction to ensure
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// that all registers are renamed as a group.
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if (MI->getOpcode() == TargetInstrInfo::KILL) {
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DEBUG(errs() << "\tKill Group:");
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unsigned FirstReg = 0;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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if (FirstReg != 0) {
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DEBUG(errs() << "=" << TRI->getName(Reg));
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UnionGroups(FirstReg, Reg);
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} else {
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DEBUG(errs() << " " << TRI->getName(Reg));
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FirstReg = Reg;
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}
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}
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DEBUG(errs() << "->g" << GetGroup(FirstReg) << '\n');
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}
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}
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BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
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BitVector BV(TRI->getNumRegs(), false);
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bool first = true;
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// Check all references that need rewriting for Reg. For each, use
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// the corresponding register class to narrow the set of registers
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// that are appropriate for renaming.
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std::pair<std::multimap<unsigned, RegisterReference>::iterator,
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std::multimap<unsigned, RegisterReference>::iterator>
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Range = RegRefs.equal_range(Reg);
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for (std::multimap<unsigned, RegisterReference>::iterator
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Q = Range.first, QE = Range.second; Q != QE; ++Q) {
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const TargetRegisterClass *RC = Q->second.RC;
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if (RC == NULL) continue;
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BitVector RCBV = TRI->getAllocatableSet(MF, RC);
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if (first) {
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BV |= RCBV;
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first = false;
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} else {
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BV &= RCBV;
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}
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DEBUG(errs() << " " << RC->getName());
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}
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return BV;
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}
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bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
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unsigned AntiDepGroupIndex,
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std::map<unsigned, unsigned> &RenameMap) {
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// Collect all registers in the same group as AntiDepReg. These all
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// need to be renamed together if we are to break the
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// anti-dependence.
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std::vector<unsigned> Regs;
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GetGroupRegs(AntiDepGroupIndex, Regs);
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assert(Regs.size() > 0 && "Empty register group!");
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if (Regs.size() == 0)
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return false;
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// Find the "superest" register in the group. At the same time,
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// collect the BitVector of registers that can be used to rename
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// each register.
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DEBUG(errs() << "\tRename Candidates for Group g" << AntiDepGroupIndex << ":\n");
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std::map<unsigned, BitVector> RenameRegisterMap;
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unsigned SuperReg = 0;
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for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
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unsigned Reg = Regs[i];
|
||||
if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
|
||||
SuperReg = Reg;
|
||||
|
||||
// If Reg has any references, then collect possible rename regs
|
||||
if (RegRefs.count(Reg) > 0) {
|
||||
DEBUG(errs() << "\t\t" << TRI->getName(Reg) << ":");
|
||||
|
||||
BitVector BV = GetRenameRegisters(Reg);
|
||||
RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
|
||||
|
||||
DEBUG(errs() << " ::");
|
||||
DEBUG(for (int r = BV.find_first(); r != -1; r = BV.find_next(r))
|
||||
errs() << " " << TRI->getName(r));
|
||||
DEBUG(errs() << "\n");
|
||||
}
|
||||
}
|
||||
|
||||
// All group registers should be a subreg of SuperReg.
|
||||
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
||||
unsigned Reg = Regs[i];
|
||||
if (Reg == SuperReg) continue;
|
||||
bool IsSub = TRI->isSubRegister(SuperReg, Reg);
|
||||
assert(IsSub && "Expecting group subregister");
|
||||
if (!IsSub)
|
||||
return false;
|
||||
}
|
||||
|
||||
// FIXME: for now just handle single register in group case...
|
||||
if (Regs.size() > 1)
|
||||
return false;
|
||||
|
||||
// Check each possible rename register for SuperReg. If that register
|
||||
// is available, and the corresponding registers are available for
|
||||
// the other group subregisters, then we can use those registers to
|
||||
// rename.
|
||||
DEBUG(errs() << "\tFind Register:");
|
||||
BitVector SuperBV = RenameRegisterMap[SuperReg];
|
||||
for (int r = SuperBV.find_first(); r != -1; r = SuperBV.find_next(r)) {
|
||||
const unsigned Reg = (unsigned)r;
|
||||
// Don't replace a register with itself.
|
||||
if (Reg == SuperReg) continue;
|
||||
|
||||
DEBUG(errs() << " " << TRI->getName(Reg));
|
||||
|
||||
// If Reg is dead and Reg's most recent def is not before
|
||||
// SuperRegs's kill, it's safe to replace SuperReg with
|
||||
// Reg. We must also check all subregisters of Reg.
|
||||
if (IsLive(Reg) || (KillIndices[SuperReg] > DefIndices[Reg])) {
|
||||
DEBUG(errs() << "(live)");
|
||||
continue;
|
||||
} else {
|
||||
bool found = false;
|
||||
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
|
||||
*Subreg; ++Subreg) {
|
||||
unsigned SubregReg = *Subreg;
|
||||
if (IsLive(SubregReg) || (KillIndices[SuperReg] > DefIndices[SubregReg])) {
|
||||
DEBUG(errs() << "(subreg " << TRI->getName(SubregReg) << " live)");
|
||||
found = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (found)
|
||||
continue;
|
||||
}
|
||||
|
||||
if (Reg != 0) {
|
||||
DEBUG(errs() << '\n');
|
||||
RenameMap.insert(std::pair<unsigned, unsigned>(SuperReg, Reg));
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
DEBUG(errs() << '\n');
|
||||
|
||||
// No registers are free and available!
|
||||
return false;
|
||||
}
|
||||
|
||||
/// BreakAntiDependencies - Identifiy anti-dependencies within the
|
||||
/// ScheduleDAG and break them by renaming registers.
|
||||
///
|
||||
unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(std::vector<SUnit>& SUnits,
|
||||
MachineBasicBlock::iterator& Begin,
|
||||
MachineBasicBlock::iterator& End,
|
||||
unsigned InsertPosIndex) {
|
||||
// The code below assumes that there is at least one instruction,
|
||||
// so just duck out immediately if the block is empty.
|
||||
if (SUnits.empty()) return false;
|
||||
|
||||
// ...need a map from MI to SUnit.
|
||||
std::map<MachineInstr *, SUnit *> MISUnitMap;
|
||||
|
||||
DEBUG(errs() << "Breaking all anti-dependencies\n");
|
||||
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
||||
SUnit *SU = &SUnits[i];
|
||||
MISUnitMap.insert(std::pair<MachineInstr *, SUnit *>(SU->getInstr(), SU));
|
||||
}
|
||||
|
||||
#ifndef NDEBUG
|
||||
{
|
||||
DEBUG(errs() << "Available regs:");
|
||||
for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
|
||||
if (!IsLive(Reg))
|
||||
DEBUG(errs() << " " << TRI->getName(Reg));
|
||||
}
|
||||
DEBUG(errs() << '\n');
|
||||
}
|
||||
#endif
|
||||
|
||||
// Attempt to break anti-dependence edges. Walk the instructions
|
||||
// from the bottom up, tracking information about liveness as we go
|
||||
// to help determine which registers are available.
|
||||
unsigned Broken = 0;
|
||||
unsigned Count = InsertPosIndex - 1;
|
||||
for (MachineBasicBlock::iterator I = End, E = Begin;
|
||||
I != E; --Count) {
|
||||
MachineInstr *MI = --I;
|
||||
|
||||
DEBUG(errs() << "Anti: ");
|
||||
DEBUG(MI->dump());
|
||||
|
||||
std::set<unsigned> PassthruRegs;
|
||||
GetPassthruRegs(MI, PassthruRegs);
|
||||
|
||||
// Process the defs in MI...
|
||||
PrescanInstruction(MI, Count, PassthruRegs);
|
||||
|
||||
std::vector<SDep*> Edges;
|
||||
SUnit *PathSU = MISUnitMap[MI];
|
||||
if (PathSU)
|
||||
AntiDepPathStep(PathSU, Edges);
|
||||
|
||||
// Ignore KILL instructions (they form a group in ScanInstruction
|
||||
// but don't cause any anti-dependence breaking themselves)
|
||||
if (MI->getOpcode() != TargetInstrInfo::KILL) {
|
||||
// Attempt to break each anti-dependency...
|
||||
for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
|
||||
SDep *Edge = Edges[i];
|
||||
SUnit *NextSU = Edge->getSUnit();
|
||||
|
||||
if (Edge->getKind() != SDep::Anti) continue;
|
||||
|
||||
unsigned AntiDepReg = Edge->getReg();
|
||||
DEBUG(errs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
|
||||
assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
|
||||
|
||||
if (!AllocatableSet.test(AntiDepReg)) {
|
||||
// Don't break anti-dependencies on non-allocatable registers.
|
||||
DEBUG(errs() << " (non-allocatable)\n");
|
||||
continue;
|
||||
} else if (PassthruRegs.count(AntiDepReg) != 0) {
|
||||
// If the anti-dep register liveness "passes-thru", then
|
||||
// don't try to change it. It will be changed along with
|
||||
// the use if required to break an earlier antidep.
|
||||
DEBUG(errs() << " (passthru)\n");
|
||||
continue;
|
||||
} else {
|
||||
// No anti-dep breaking for implicit deps
|
||||
MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg);
|
||||
assert(AntiDepOp != NULL && "Can't find index for defined register operand");
|
||||
if ((AntiDepOp == NULL) || AntiDepOp->isImplicit()) {
|
||||
DEBUG(errs() << " (implicit)\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
// If the SUnit has other dependencies on the SUnit that
|
||||
// it anti-depends on, don't bother breaking the
|
||||
// anti-dependency since those edges would prevent such
|
||||
// units from being scheduled past each other
|
||||
// regardless.
|
||||
for (SUnit::pred_iterator P = PathSU->Preds.begin(),
|
||||
PE = PathSU->Preds.end(); P != PE; ++P) {
|
||||
if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti)) {
|
||||
DEBUG(errs() << " (real dependency)\n");
|
||||
AntiDepReg = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (AntiDepReg == 0) continue;
|
||||
}
|
||||
|
||||
assert(AntiDepReg != 0);
|
||||
if (AntiDepReg == 0) continue;
|
||||
|
||||
// Determine AntiDepReg's register group.
|
||||
const unsigned GroupIndex = GetGroup(AntiDepReg);
|
||||
if (GroupIndex == 0) {
|
||||
DEBUG(errs() << " (zero group)\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
DEBUG(errs() << '\n');
|
||||
|
||||
// Look for a suitable register to use to break the anti-dependence.
|
||||
std::map<unsigned, unsigned> RenameMap;
|
||||
if (FindSuitableFreeRegisters(GroupIndex, RenameMap)) {
|
||||
DEBUG(errs() << "\tBreaking anti-dependence edge on "
|
||||
<< TRI->getName(AntiDepReg) << ":");
|
||||
|
||||
// Handle each group register...
|
||||
for (std::map<unsigned, unsigned>::iterator
|
||||
S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
|
||||
unsigned CurrReg = S->first;
|
||||
unsigned NewReg = S->second;
|
||||
|
||||
DEBUG(errs() << " " << TRI->getName(CurrReg) << "->" <<
|
||||
TRI->getName(NewReg) << "(" <<
|
||||
RegRefs.count(CurrReg) << " refs)");
|
||||
|
||||
// Update the references to the old register CurrReg to
|
||||
// refer to the new register NewReg.
|
||||
std::pair<std::multimap<unsigned, RegisterReference>::iterator,
|
||||
std::multimap<unsigned, RegisterReference>::iterator>
|
||||
Range = RegRefs.equal_range(CurrReg);
|
||||
for (std::multimap<unsigned, RegisterReference>::iterator
|
||||
Q = Range.first, QE = Range.second; Q != QE; ++Q) {
|
||||
Q->second.Operand->setReg(NewReg);
|
||||
}
|
||||
|
||||
// We just went back in time and modified history; the
|
||||
// liveness information for CurrReg is now inconsistent. Set
|
||||
// the state as if it were dead.
|
||||
UnionGroups(NewReg, 0);
|
||||
RegRefs.erase(NewReg);
|
||||
DefIndices[NewReg] = DefIndices[CurrReg];
|
||||
KillIndices[NewReg] = KillIndices[CurrReg];
|
||||
|
||||
UnionGroups(CurrReg, 0);
|
||||
RegRefs.erase(CurrReg);
|
||||
DefIndices[CurrReg] = KillIndices[CurrReg];
|
||||
KillIndices[CurrReg] = ~0u;
|
||||
assert(((KillIndices[CurrReg] == ~0u) !=
|
||||
(DefIndices[CurrReg] == ~0u)) &&
|
||||
"Kill and Def maps aren't consistent for AntiDepReg!");
|
||||
}
|
||||
|
||||
++Broken;
|
||||
DEBUG(errs() << '\n');
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ScanInstruction(MI, Count);
|
||||
}
|
||||
|
||||
return Broken;
|
||||
}
|
||||
136
lib/CodeGen/AggressiveAntiDepBreaker.h
Normal file
136
lib/CodeGen/AggressiveAntiDepBreaker.h
Normal file
@ -0,0 +1,136 @@
|
||||
//=- llvm/CodeGen/AggressiveAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file implements the AggressiveAntiDepBreaker class, which
|
||||
// implements register anti-dependence breaking during post-RA
|
||||
// scheduling. It attempts to break all anti-dependencies within a
|
||||
// block.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef LLVM_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
|
||||
#define LLVM_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H
|
||||
|
||||
#include "llvm/CodeGen/AntiDepBreaker.h"
|
||||
#include "llvm/CodeGen/MachineBasicBlock.h"
|
||||
#include "llvm/CodeGen/MachineFrameInfo.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
||||
#include "llvm/CodeGen/ScheduleDAG.h"
|
||||
#include "llvm/Target/TargetRegisterInfo.h"
|
||||
#include "llvm/ADT/BitVector.h"
|
||||
#include "llvm/ADT/SmallSet.h"
|
||||
|
||||
namespace llvm {
|
||||
class AggressiveAntiDepBreaker : public AntiDepBreaker {
|
||||
MachineFunction& MF;
|
||||
MachineRegisterInfo &MRI;
|
||||
const TargetRegisterInfo *TRI;
|
||||
|
||||
/// RegisterReference - Information about a register reference
|
||||
/// within a liverange
|
||||
typedef struct {
|
||||
/// Operand - The registers operand
|
||||
MachineOperand *Operand;
|
||||
/// RC - The register class
|
||||
const TargetRegisterClass *RC;
|
||||
} RegisterReference;
|
||||
|
||||
/// AllocatableSet - The set of allocatable registers.
|
||||
/// We'll be ignoring anti-dependencies on non-allocatable registers,
|
||||
/// because they may not be safe to break.
|
||||
const BitVector AllocatableSet;
|
||||
|
||||
/// GroupNodes - Implements a disjoint-union data structure to
|
||||
/// form register groups. A node is represented by an index into
|
||||
/// the vector. A node can "point to" itself to indicate that it
|
||||
/// is the parent of a group, or point to another node to indicate
|
||||
/// that it is a member of the same group as that node.
|
||||
std::vector<unsigned> GroupNodes;
|
||||
|
||||
/// GroupNodeIndices - For each register, the index of the GroupNode
|
||||
/// currently representing the group that the register belongs to.
|
||||
/// Register 0 is always represented by the 0 group, a group
|
||||
/// composed of registers that are not eligible for anti-aliasing.
|
||||
unsigned GroupNodeIndices[TargetRegisterInfo::FirstVirtualRegister];
|
||||
|
||||
/// RegRegs - Map registers to all their references within a live range.
|
||||
std::multimap<unsigned, RegisterReference> RegRefs;
|
||||
|
||||
/// KillIndices - The index of the most recent kill (proceding bottom-up),
|
||||
/// or ~0u if the register is not live.
|
||||
unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
|
||||
|
||||
/// DefIndices - The index of the most recent complete def (proceding bottom
|
||||
/// up), or ~0u if the register is live.
|
||||
unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
|
||||
|
||||
public:
|
||||
AggressiveAntiDepBreaker(MachineFunction& MFi);
|
||||
~AggressiveAntiDepBreaker();
|
||||
|
||||
/// Start - Initialize anti-dep breaking for a new basic block.
|
||||
void StartBlock(MachineBasicBlock *BB);
|
||||
|
||||
/// BreakAntiDependencies - Identifiy anti-dependencies along the critical path
|
||||
/// of the ScheduleDAG and break them by renaming registers.
|
||||
///
|
||||
unsigned BreakAntiDependencies(std::vector<SUnit>& SUnits,
|
||||
MachineBasicBlock::iterator& Begin,
|
||||
MachineBasicBlock::iterator& End,
|
||||
unsigned InsertPosIndex);
|
||||
|
||||
/// Observe - Update liveness information to account for the current
|
||||
/// instruction, which will not be scheduled.
|
||||
///
|
||||
void Observe(MachineInstr *MI, unsigned Count, unsigned InsertPosIndex);
|
||||
|
||||
/// Finish - Finish anti-dep breaking for a basic block.
|
||||
void FinishBlock();
|
||||
|
||||
private:
|
||||
// GetGroup - Get the group for a register. The returned value is
|
||||
// the index of the GroupNode representing the group.
|
||||
unsigned GetGroup(unsigned Reg);
|
||||
|
||||
// GetGroupRegs - Return a vector of the registers belonging to a
|
||||
// group.
|
||||
void GetGroupRegs(unsigned Group, std::vector<unsigned> &Regs);
|
||||
|
||||
// UnionGroups - Union Reg1's and Reg2's groups to form a new
|
||||
// group. Return the index of the GroupNode representing the
|
||||
// group.
|
||||
unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
|
||||
|
||||
// LeaveGroup - Remove a register from its current group and place
|
||||
// it alone in its own group. Return the index of the GroupNode
|
||||
// representing the registers new group.
|
||||
unsigned LeaveGroup(unsigned Reg);
|
||||
|
||||
/// IsLive - Return true if Reg is live
|
||||
bool IsLive(unsigned Reg);
|
||||
|
||||
/// IsImplicitDefUse - Return true if MO represents a register
|
||||
/// that is both implicitly used and defined in MI
|
||||
bool IsImplicitDefUse(MachineInstr *MI, MachineOperand& MO);
|
||||
|
||||
/// GetPassthruRegs - If MI implicitly def/uses a register, then
|
||||
/// return that register and all subregisters.
|
||||
void GetPassthruRegs(MachineInstr *MI, std::set<unsigned>& PassthruRegs);
|
||||
|
||||
void PrescanInstruction(MachineInstr *MI, unsigned Count,
|
||||
std::set<unsigned>& PassthruRegs);
|
||||
void ScanInstruction(MachineInstr *MI, unsigned Count);
|
||||
BitVector GetRenameRegisters(unsigned Reg);
|
||||
bool FindSuitableFreeRegisters(unsigned AntiDepGroupIndex,
|
||||
std::map<unsigned, unsigned> &RenameMap);
|
||||
};
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -1,4 +1,5 @@
|
||||
add_llvm_library(LLVMCodeGen
|
||||
AggressiveAntiDepBreaker.cpp
|
||||
BranchFolding.cpp
|
||||
CodePlacementOpt.cpp
|
||||
CriticalAntiDepBreaker.cpp
|
||||
|
||||
@ -19,6 +19,7 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#define DEBUG_TYPE "post-RA-sched"
|
||||
#include "AggressiveAntiDepBreaker.h"
|
||||
#include "CriticalAntiDepBreaker.h"
|
||||
#include "ExactHazardRecognizer.h"
|
||||
#include "SimpleHazardRecognizer.h"
|
||||
@ -236,9 +237,10 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
|
||||
(ScheduleHazardRecognizer *)new ExactHazardRecognizer(InstrItins) :
|
||||
(ScheduleHazardRecognizer *)new SimpleHazardRecognizer();
|
||||
AntiDepBreaker *ADB =
|
||||
(AntiDepMode == TargetSubtarget::ANTIDEP_ALL) ? NULL /* FIXME */ :
|
||||
(AntiDepMode == TargetSubtarget::ANTIDEP_CRITICAL) ?
|
||||
new CriticalAntiDepBreaker(Fn) : NULL;
|
||||
((AntiDepMode == TargetSubtarget::ANTIDEP_ALL) ?
|
||||
(AntiDepBreaker *)new AggressiveAntiDepBreaker(Fn) :
|
||||
((AntiDepMode == TargetSubtarget::ANTIDEP_CRITICAL) ?
|
||||
(AntiDepBreaker *)new CriticalAntiDepBreaker(Fn) : NULL));
|
||||
|
||||
SchedulePostRATDList Scheduler(Fn, MLI, MDT, HR, ADB, AA);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user