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PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually

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improves the generated code in some cases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109985 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2010-08-01 21:13:28 +00:00
parent ad2b04c07f
commit 348e02600e
2 changed files with 13 additions and 2 deletions
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4
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
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@ -113,8 +113,8 @@ namespace {
static uint64_t getNearPower2(uint64_t x) {
if (!x) return 0;
unsigned at = CountLeadingZeros_64(x);
uint64_t complow = 1 << (63 - at);
uint64_t comphigh = 1 << (64 - at);
uint64_t complow = 1ULL << (63 - at);
uint64_t comphigh = 1ULL << (64 - at);
//cerr << x << ":" << complow << ":" << comphigh << "\n";
if (abs64(complow - x) <= abs64(comphigh - x))
return complow;

11
test/CodeGen/Alpha/2010-08-01-mulreduce64.ll Normal file
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@ -0,0 +1,11 @@
; RUN: llc < %s -march=alpha | FileCheck %s
define fastcc i64 @getcount(i64 %s) {
%tmp431 = mul i64 %s, 12884901888
ret i64 %tmp431
}
; CHECK: sll $16,33,$0
; CHECK-NEXT: sll $16,32,$1
; CHECK-NEXT: addq $0,$1,$0