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[X86] Fix a bug in X86's peephole optimization.
Peephole optimization was folding MOVSDrm, which is a zero-extending double precision floating point load, into ADDPDrr, which is a SIMD add of two packed double precision floating point values. (before) %vreg21<def> = MOVSDrm <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%7](align=16)(tbaa=<badref>) VR128:%vreg21 %vreg23<def,tied1> = ADDPDrr %vreg20<tied0>, %vreg21; VR128:%vreg23,%vreg20,%vreg21 (after) %vreg23<def,tied1> = ADDPDrm %vreg20<tied0>, <fi#0>, 1, %noreg, 0, %noreg; mem:LD8[%7](align=16)(tbaa=<badref>) VR128:%vreg23,%vreg20 X86InstrInfo::foldMemoryOperandImpl already had the logic that prevented this from happening. However the check wasn't being conducted for loads from stack objects. This commit factors out the logic into a new function and uses it for checking loads from stack slots are not zero-extending loads. rdar://problem/18236850 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217799 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4423,6 +4423,25 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
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}
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static bool isPartialRegisterLoad(const MachineInstr &LoadMI,
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const MachineFunction &MF) {
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unsigned Opc = LoadMI.getOpcode();
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unsigned RegSize =
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MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
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if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4)
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// These instructions only load 32 bits, we can't fold them if the
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// destination register is wider than 32 bits (4 bytes).
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return true;
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if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8)
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// These instructions only load 64 bits, we can't fold them if the
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// destination register is wider than 64 bits (8 bytes).
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return true;
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return false;
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}
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MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops,
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@ -4430,8 +4449,11 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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// If loading from a FrameIndex, fold directly from the FrameIndex.
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unsigned NumOps = LoadMI->getDesc().getNumOperands();
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int FrameIndex;
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if (isLoadFromStackSlot(LoadMI, FrameIndex))
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if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
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if (isPartialRegisterLoad(*LoadMI, MF))
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return nullptr;
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return foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
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}
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// Check switch flag
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if (NoFusing) return nullptr;
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@ -4542,19 +4564,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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break;
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}
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default: {
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if ((LoadMI->getOpcode() == X86::MOVSSrm ||
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LoadMI->getOpcode() == X86::VMOVSSrm) &&
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MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
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> 4)
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// These instructions only load 32 bits, we can't fold them if the
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// destination register is wider than 32 bits (4 bytes).
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return nullptr;
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if ((LoadMI->getOpcode() == X86::MOVSDrm ||
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LoadMI->getOpcode() == X86::VMOVSDrm) &&
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MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
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> 8)
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// These instructions only load 64 bits, we can't fold them if the
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// destination register is wider than 64 bits (8 bytes).
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if (isPartialRegisterLoad(*LoadMI, MF))
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return nullptr;
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// Folding a normal load. Just copy the load's address operands.
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31
test/CodeGen/X86/peephole-fold-movsd.ll
Normal file
31
test/CodeGen/X86/peephole-fold-movsd.ll
Normal file
@ -0,0 +1,31 @@
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; RUN: llc -march=x86-64 < %s | FileCheck %s
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;
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; Check that x86's peephole optimization doesn't fold a 64-bit load (movsd) into
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; addpd.
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; rdar://problem/18236850
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%struct.S1 = type { double, double }
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@g = common global %struct.S1 zeroinitializer, align 8
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declare void @foo3(%struct.S1*)
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; CHECK: movsd (%rsp), [[R0:%xmm[0-9]+]]
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; CHECK: addpd [[R0]], %xmm{{[0-9]+}}
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define void @foo1(double %a.coerce0, double %a.coerce1, double %b.coerce0, double %b.coerce1) {
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%1 = alloca <2 x double>, align 16
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%tmpcast = bitcast <2 x double>* %1 to %struct.S1*
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call void @foo3(%struct.S1* %tmpcast) #2
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%p2 = getelementptr inbounds %struct.S1* %tmpcast, i64 0, i32 0
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%2 = load double* %p2, align 16
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%p3 = getelementptr inbounds %struct.S1* %tmpcast, i64 0, i32 1
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%3 = load double* %p3, align 8
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%4 = insertelement <2 x double> undef, double %2, i32 0
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%5 = insertelement <2 x double> %4, double 0.000000e+00, i32 1
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%6 = insertelement <2 x double> undef, double %3, i32 1
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%7 = insertelement <2 x double> %6, double 1.000000e+00, i32 0
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%8 = fadd <2 x double> %5, %7
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store <2 x double> %8, <2 x double>* bitcast (%struct.S1* @g to <2 x double>*), align 16
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ret void
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}
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