From 349c4952009525b27383e2120a6b3c998f39bd09 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 7 Jan 2008 03:13:06 +0000 Subject: [PATCH] Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetInstrInfo.h | 105 ++++++++---------- lib/CodeGen/LiveVariables.cpp | 3 +- lib/CodeGen/MachineInstr.cpp | 24 ++-- lib/CodeGen/PrologEpilogInserter.cpp | 5 +- lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 29 ++--- .../SelectionDAG/ScheduleDAGRRList.cpp | 19 ++-- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 +- lib/CodeGen/TwoAddressInstructionPass.cpp | 4 +- lib/CodeGen/VirtRegMap.cpp | 2 +- lib/Target/ARM/ARMInstrInfo.cpp | 6 +- lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 2 +- lib/Target/Mips/MipsInstrInfo.cpp | 4 +- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 2 +- lib/Target/PowerPC/PPCRegisterInfo.cpp | 3 +- lib/Target/TargetInstrInfo.cpp | 2 +- lib/Target/X86/X86CodeEmitter.cpp | 4 +- lib/Target/X86/X86FloatingPoint.cpp | 8 +- lib/Target/X86/X86InstrInfo.cpp | 14 +-- 18 files changed, 115 insertions(+), 123 deletions(-) diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index d8aff40fa1c..1046e98a354 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -169,8 +169,8 @@ public: class TargetInstrDescriptor { public: unsigned short Opcode; // The opcode. - unsigned short numOperands; // Num of args (may be more if variable_ops). - unsigned short numDefs; // Num of args that are definitions. + unsigned short NumOperands; // Num of args (may be more if variable_ops). + unsigned short NumDefs; // Num of args that are definitions. const char * Name; // Assembly language mnemonic for the opcode. unsigned SchedClass; // enum identifying instr sched class unsigned Flags; // flags identifying machine instr class @@ -183,9 +183,9 @@ public: /// it is set. Returns -1 if it is not set. int getOperandConstraint(unsigned OpNum, TOI::OperandConstraint Constraint) const { - assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) && + assert((OpNum < NumOperands || hasVariableOperands()) && "Invalid operand # of TargetInstrInfo"); - if (OpNum < numOperands && + if (OpNum < NumOperands && (OpInfo[OpNum].Constraints & (1 << Constraint))) { unsigned Pos = 16 + Constraint * 4; return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; @@ -197,18 +197,50 @@ public: /// dest operand. Returns -1 if there isn't one. int findTiedToSrcOperand(unsigned OpNum) const; + const char *getName() const { + return Name; + } + + unsigned getNumOperands() const { + return NumOperands; + } + + unsigned getNumDefs() const { + return NumDefs; + } + + bool hasVariableOperands() const { + return Flags & M_VARIABLE_OPS; + } + + bool hasOptionalDef() const { + return Flags & M_HAS_OPTIONAL_DEF; + } + + const unsigned *getImplicitUses() const { + return ImplicitUses; + } + + const unsigned *getImplicitDefs() const { + return ImplicitDefs; + } + + bool isReturn() const { + return Flags & M_RET_FLAG; + } + bool isCall() const { return Flags & M_CALL_FLAG; } - bool isBranch() const { - return Flags & M_BRANCH_FLAG; - } - bool isTerminator() const { return Flags & M_TERMINATOR_FLAG; } + bool isBranch() const { + return Flags & M_BRANCH_FLAG; + } + bool isIndirectBranch() const { return Flags & M_INDIRECT_FLAG; } @@ -221,7 +253,16 @@ public: return Flags & M_NOT_DUPLICABLE; } + bool isCommutableInstr() const { + return Flags & M_COMMUTABLE; + } + /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires + /// custom insertion support when the DAG scheduler is inserting it into a + /// machine basic block. + bool usesCustomDAGSchedInsertionHook() const { + return Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; + } /// isSimpleLoad - Return true for instructions that are simple loads from /// memory. This should only be set on instructions that load a value from @@ -293,54 +334,6 @@ public: return desc[Opcode]; } - const char *getName(unsigned Opcode) const { - return get(Opcode).Name; - } - - int getNumOperands(unsigned Opcode) const { - return get(Opcode).numOperands; - } - - int getNumDefs(unsigned Opcode) const { - return get(Opcode).numDefs; - } - - const unsigned *getImplicitUses(unsigned Opcode) const { - return get(Opcode).ImplicitUses; - } - - const unsigned *getImplicitDefs(unsigned Opcode) const { - return get(Opcode).ImplicitDefs; - } - - - // - // Query instruction class flags according to the machine-independent - // flags listed above. - // - bool isReturn(unsigned Opcode) const { - return get(Opcode).Flags & M_RET_FLAG; - } - - bool isCommutableInstr(unsigned Opcode) const { - return get(Opcode).Flags & M_COMMUTABLE; - } - - /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires - /// custom insertion support when the DAG scheduler is inserting it into a - /// machine basic block. - bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { - return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; - } - - bool hasVariableOperands(unsigned Opcode) const { - return get(Opcode).Flags & M_VARIABLE_OPS; - } - - bool hasOptionalDef(unsigned Opcode) const { - return get(Opcode).Flags & M_HAS_OPTIONAL_DEF; - } - /// isTriviallyReMaterializable - Return true if the instruction is trivially /// rematerializable, meaning it has no side effects and requires no operands /// that aren't always available. diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index e1ae37cad21..1e692c5d739 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -431,7 +431,6 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) { bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { MF = &mf; - const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); RegInfo = MF->getTarget().getRegisterInfo(); assert(RegInfo && "Target doesn't have register information?"); @@ -536,7 +535,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { // Finally, if the last instruction in the block is a return, make sure to mark // it as using all of the live-out values in the function. - if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) { + if (!MBB->empty() && MBB->back().getDesc()->isReturn()) { MachineInstr *Ret = &MBB->back(); for (MachineRegisterInfo::liveout_iterator I = MF->getRegInfo().liveout_begin(), diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 49b7ef26822..99bc22230c3 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -252,13 +252,13 @@ void MachineInstr::addImplicitDefUseOperands() { /// instructions with variable number of operands). MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp) : TID(&tid), NumImplicitOps(0), Parent(0) { - if (!NoImp && TID->ImplicitDefs) - for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) + if (!NoImp && TID->getImplicitDefs()) + for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) NumImplicitOps++; - if (!NoImp && TID->ImplicitUses) - for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) + if (!NoImp && TID->getImplicitUses()) + for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) NumImplicitOps++; - Operands.reserve(NumImplicitOps + TID->numOperands); + Operands.reserve(NumImplicitOps + TID->getNumOperands()); if (!NoImp) addImplicitDefUseOperands(); // Make sure that we get added to a machine basicblock @@ -273,12 +273,12 @@ MachineInstr::MachineInstr(MachineBasicBlock *MBB, : TID(&tid), NumImplicitOps(0), Parent(0) { assert(MBB && "Cannot use inserting ctor with null basic block!"); if (TID->ImplicitDefs) - for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) + for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) NumImplicitOps++; if (TID->ImplicitUses) - for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) + for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) NumImplicitOps++; - Operands.reserve(NumImplicitOps + TID->numOperands); + Operands.reserve(NumImplicitOps + TID->getNumOperands()); addImplicitDefUseOperands(); // Make sure that we get added to a machine basicblock LeakDetector::addGarbageObject(this); @@ -487,8 +487,8 @@ MachineInstr *MachineInstr::removeFromParent() { /// OperandComplete - Return true if it's illegal to add a new operand /// bool MachineInstr::OperandsComplete() const { - unsigned short NumOperands = TID->numOperands; - if ((TID->Flags & M_VARIABLE_OPS) == 0 && + unsigned short NumOperands = TID->getNumOperands(); + if (TID->hasVariableOperands() == 0 && getNumOperands()-NumImplicitOps >= NumOperands) return true; // Broken: we have all the operands of this instruction! return false; @@ -497,8 +497,8 @@ bool MachineInstr::OperandsComplete() const { /// getNumExplicitOperands - Returns the number of non-implicit operands. /// unsigned MachineInstr::getNumExplicitOperands() const { - unsigned NumOperands = TID->numOperands; - if ((TID->Flags & M_VARIABLE_OPS) == 0) + unsigned NumOperands = TID->getNumOperands(); + if (TID->hasVariableOperands() == 0) return NumOperands; for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) { diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp index d7c0a7b9075..0f2da0bc387 100644 --- a/lib/CodeGen/PrologEpilogInserter.cpp +++ b/lib/CodeGen/PrologEpilogInserter.cpp @@ -262,7 +262,7 @@ void PEI::saveCalleeSavedRegisters(MachineFunction &Fn) { // Add code to restore the callee-save registers in each exiting block. for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI) // If last instruction is a return instruction, add an epilogue. - if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) { + if (!FI->empty() && FI->back().getDesc()->isReturn()) { MBB = FI; I = MBB->end(); --I; @@ -483,10 +483,9 @@ void PEI::insertPrologEpilogCode(MachineFunction &Fn) { Fn.getTarget().getRegisterInfo()->emitPrologue(Fn); // Add epilogue to restore the callee-save registers in each exiting block - const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { // If last instruction is a return instruction, add an epilogue - if (!I->empty() && TII.isReturn(I->back().getOpcode())) + if (!I->empty() && I->back().getDesc()->isReturn()) Fn.getTarget().getRegisterInfo()->emitEpilogue(Fn, *I); } } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 3235f4aa492..499c2c7286b 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -52,8 +52,8 @@ static void CheckForPhysRegDependency(SDNode *Def, SDNode *Use, unsigned Op, unsigned ResNo = Use->getOperand(2).ResNo; if (Def->isTargetOpcode()) { const TargetInstrDescriptor &II = TII->get(Def->getTargetOpcode()); - if (ResNo >= II.numDefs && - II.ImplicitDefs[ResNo - II.numDefs] == Reg) { + if (ResNo >= II.getNumDefs() && + II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { PhysReg = Reg; const TargetRegisterClass *RC = MRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg); @@ -149,7 +149,7 @@ void ScheduleDAG::BuildSchedUnits() { if (MainNode->isTargetOpcode()) { unsigned Opc = MainNode->getTargetOpcode(); const TargetInstrDescriptor &TID = TII->get(Opc); - for (unsigned i = 0; i != TID.numOperands; ++i) { + for (unsigned i = 0; i != TID.getNumOperands(); ++i) { if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { SU->isTwoAddress = true; break; @@ -166,8 +166,8 @@ void ScheduleDAG::BuildSchedUnits() { for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) { SDNode *N = SU->FlaggedNodes[n]; if (N->isTargetOpcode() && - TII->getImplicitDefs(N->getTargetOpcode()) && - CountResults(N) > (unsigned)TII->getNumDefs(N->getTargetOpcode())) + TII->get(N->getTargetOpcode()).getImplicitDefs() && + CountResults(N) > TII->get(N->getTargetOpcode()).getNumDefs()) SU->hasPhysRegDefs = true; for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { @@ -293,7 +293,7 @@ static const TargetRegisterClass *getInstrOperandRegClass( const TargetInstrInfo *TII, const TargetInstrDescriptor *II, unsigned Op) { - if (Op >= II->numOperands) { + if (Op >= II->getNumOperands()) { assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction"); return NULL; } @@ -373,7 +373,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, const TargetInstrDescriptor &II, DenseMap &VRBaseMap) { - for (unsigned i = 0; i < II.numDefs; ++i) { + for (unsigned i = 0; i < II.getNumDefs(); ++i) { // If the specific node value is only used by a CopyToReg and the dest reg // is a vreg, use the CopyToReg'd destination register instead of creating // a new vreg. @@ -435,7 +435,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, // Get/emit the operand. unsigned VReg = getVR(Op, VRBaseMap); const TargetInstrDescriptor *TID = MI->getDesc(); - bool isOptDef = (IIOpNum < TID->numOperands) + bool isOptDef = (IIOpNum < TID->getNumOperands()) ? (TID->OpInfo[IIOpNum].isOptionalDef()) : false; MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef)); @@ -674,10 +674,11 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, unsigned NumResults = CountResults(Node); unsigned NodeOperands = CountOperands(Node); unsigned NumMIOperands = NodeOperands + NumResults; - bool HasPhysRegOuts = (NumResults > II.numDefs) && II.ImplicitDefs; + bool HasPhysRegOuts = (NumResults > II.getNumDefs()) && + II.getImplicitDefs() != 0; #ifndef NDEBUG - assert((unsigned(II.numOperands) == NumMIOperands || - HasPhysRegOuts || (II.Flags & M_VARIABLE_OPS)) && + assert((II.getNumOperands() == NumMIOperands || + HasPhysRegOuts || II.hasVariableOperands()) && "#operands for dag node doesn't match .td file!"); #endif @@ -692,7 +693,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, // Emit all of the actual operands of this instruction, adding them to the // instruction as appropriate. for (unsigned i = 0; i != NodeOperands; ++i) - AddOperand(MI, Node->getOperand(i), i+II.numDefs, &II, VRBaseMap); + AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap); // Commute node if it has been determined to be profitable. if (CommuteSet.count(Node)) { @@ -719,8 +720,8 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, // Additional results must be an physical register def. if (HasPhysRegOuts) { - for (unsigned i = II.numDefs; i < NumResults; ++i) { - unsigned Reg = II.ImplicitDefs[i - II.numDefs]; + for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { + unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; if (Node->hasAnyUseOfValue(i)) EmitCopyFromReg(Node, i, InstanceNo, Reg, VRBaseMap); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index fcc2b8af28d..846004e2138 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -148,7 +148,7 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() { if (!SU || !SU->Node) continue; if (SU->isCommutable) { unsigned Opc = SU->Node->getTargetOpcode(); - unsigned NumRes = TII->getNumDefs(Opc); + unsigned NumRes = TII->get(Opc).getNumDefs(); unsigned NumOps = CountOperands(SU->Node); for (unsigned j = 0; j != NumOps; ++j) { if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) == -1) @@ -431,7 +431,7 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { SUnit *NewSU = NewSUnit(N); SUnitMap[N].push_back(NewSU); const TargetInstrDescriptor *TID = &TII->get(N->getTargetOpcode()); - for (unsigned i = 0; i != TID->numOperands; ++i) { + for (unsigned i = 0; i != TID->getNumOperands(); ++i) { if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) { NewSU->isTwoAddress = true; break; @@ -623,8 +623,8 @@ static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg, const TargetInstrInfo *TII) { const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode()); assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!"); - unsigned NumRes = TID.numDefs; - for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef) { + unsigned NumRes = TID.getNumDefs(); + for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) { if (Reg == *ImpDef) break; ++NumRes; @@ -1287,7 +1287,7 @@ template bool BURegReductionPriorityQueue::canClobber(SUnit *SU, SUnit *Op) { if (SU->isTwoAddress) { unsigned Opc = SU->Node->getTargetOpcode(); - unsigned NumRes = TII->getNumDefs(Opc); + unsigned NumRes = TII->get(Opc).getNumDefs(); unsigned NumOps = ScheduleDAG::CountOperands(SU->Node); for (unsigned i = 0; i != NumOps; ++i) { if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) != -1) { @@ -1321,11 +1321,12 @@ static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU, const TargetInstrInfo *TII, const MRegisterInfo *MRI) { SDNode *N = SuccSU->Node; - unsigned NumDefs = TII->getNumDefs(N->getTargetOpcode()); - const unsigned *ImpDefs = TII->getImplicitDefs(N->getTargetOpcode()); + unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs(); + const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs(); if (!ImpDefs) return false; - const unsigned *SUImpDefs = TII->getImplicitDefs(SU->Node->getTargetOpcode()); + const unsigned *SUImpDefs = + TII->get(SU->Node->getTargetOpcode()).getImplicitDefs(); if (!SUImpDefs) return false; for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) { @@ -1361,7 +1362,7 @@ void BURegReductionPriorityQueue::AddPseudoTwoAddrDeps() { continue; unsigned Opc = Node->getTargetOpcode(); - unsigned NumRes = TII->getNumDefs(Opc); + unsigned NumRes = TII->get(Opc).getNumDefs(); unsigned NumOps = ScheduleDAG::CountOperands(Node); for (unsigned j = 0; j != NumOps; ++j) { if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) != -1) { diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 74a506c24df..22065156497 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3602,7 +3602,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { if (G) { if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) if (getOpcode()-ISD::BUILTIN_OP_END < TII->getNumOpcodes()) - return TII->getName(getOpcode()-ISD::BUILTIN_OP_END); + return TII->get(getOpcode()-ISD::BUILTIN_OP_END).getName(); TargetLowering &TLI = G->getTargetLoweringInfo(); const char *Name = diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 9eb3d7a4deb..bc8d62e6d9b 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -96,7 +96,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { const TargetInstrDescriptor *TID = mi->getDesc(); bool FirstTied = true; - for (unsigned si = 1, e = TID->numOperands; si < e; ++si) { + for (unsigned si = 1, e = TID->getNumOperands(); si < e; ++si) { int ti = TID->getOperandConstraint(si, TOI::TIED_TO); if (ti == -1) continue; @@ -176,7 +176,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { // FIXME: This assumes there are no more operands which are tied // to another register. #ifndef NDEBUG - for (unsigned i = si+1, e = TID->numOperands; i < e; ++i) + for (unsigned i = si+1, e = TID->getNumOperands(); i < e; ++i) assert(TID->getOperandConstraint(i, TOI::TIED_TO) == -1); #endif diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 967e2926a1d..a79a4a24ea5 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -552,7 +552,7 @@ static void UpdateKills(MachineInstr &MI, BitVector &RegKills, KillOps[Reg]->setIsKill(false); KillOps[Reg] = NULL; RegKills.reset(Reg); - if (i < TID->numOperands && + if (i < TID->getNumOperands() && TID->getOperandConstraint(i, TOI::TIED_TO) == -1) // Unless it's a two-address operand, this is the new kill. MO.setIsKill(); diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index b291d19d865..fa52be8382a 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -63,7 +63,7 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI, return true; case ARM::MOVr: case ARM::tMOVr: - assert(MI.getDesc()->numOperands >= 2 && + assert(MI.getDesc()->getNumOperands() >= 2 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && "Invalid ARM MOV instruction"); @@ -201,7 +201,7 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr *MemMI = NULL; unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); const TargetInstrDescriptor *TID = MI->getDesc(); - unsigned NumOps = TID->numOperands; + unsigned NumOps = TID->getNumOperands(); bool isLoad = TID->isSimpleLoad(); const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); const MachineOperand &Base = MI->getOperand(2); @@ -897,7 +897,7 @@ unsigned ARM::GetInstSize(MachineInstr *MI) { case ARM::tBR_JTr: { // These are jumptable branches, i.e. a branch followed by an inlined // jumptable. The size is 4 + 4 * number of entries. - unsigned NumOps = TID->numOperands; + unsigned NumOps = TID->getNumOperands(); MachineOperand JTOP = MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2)); unsigned JTI = JTOP.getIndex(); diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 152e2d107fd..29da83d9d9a 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -600,7 +600,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) { unsigned PredReg = 0; ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg); const TargetInstrDescriptor *TID = MBBI->getDesc(); - unsigned OffField = MBBI->getOperand(TID->numOperands-3).getImm(); + unsigned OffField = MBBI->getOperand(TID->getNumOperands()-3).getImm(); int Offset = isAM2 ? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4; if (isAM2) { diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index cda50527bae..8896b35aed0 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -261,7 +261,7 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm()); const TargetInstrDescriptor &TID = get(Opc); - if (TID.numOperands == 3) + if (TID.getNumOperands() == 3) BuildMI(&MBB, TID).addReg(Cond[1].getReg()) .addReg(Cond[2].getReg()) .addMBB(TBB); @@ -277,7 +277,7 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm()); const TargetInstrDescriptor &TID = get(Opc); - if (TID.numOperands == 3) + if (TID.getNumOperands() == 3) BuildMI(&MBB, TID).addReg(Cond[1].getReg()) .addReg(Cond[2].getReg()) .addMBB(TBB); diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 87c698b4b13..7ab17bce1b1 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -262,7 +262,7 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { // Find all return blocks, outputting a restore in each epilog. for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { - if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) { + if (!BB->empty() && BB->back().getDesc()->isReturn()) { IP = BB->end(); --IP; // Skip over all terminator instructions, which are part of the return diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 7609e0982e9..866c2bfe469 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -538,10 +538,9 @@ static void RemoveVRSaveCode(MachineInstr *MI) { bool RemovedAllMTVRSAVEs = true; // See if we can find and remove the MTVRSAVE instruction from all of the // epilog blocks. - const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { // If last instruction is a return instruction, add an epilogue - if (!I->empty() && TII.isReturn(I->back().getOpcode())) { + if (!I->empty() && I->back().getDesc()->isReturn()) { bool FoundIt = false; for (MBBI = I->end(); MBBI != I->begin(); ) { --MBBI; diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp index ba56caa68e8..5342dd18727 100644 --- a/lib/Target/TargetInstrInfo.cpp +++ b/lib/Target/TargetInstrInfo.cpp @@ -19,7 +19,7 @@ using namespace llvm; /// findTiedToSrcOperand - Returns the operand that is tied to the specified /// dest operand. Returns -1 if there isn't one. int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const { - for (unsigned i = 0, e = numOperands; i != e; ++i) { + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { if (i == OpNum) continue; if (getOperandConstraint(i, TOI::TIED_TO) == (int)OpNum) diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 3c67d625152..c4461a751a1 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -444,7 +444,7 @@ unsigned Emitter::determineREX(const MachineInstr &MI) { if (Desc->TSFlags & X86II::REX_W) REX |= 1 << 3; - unsigned NumOps = Desc->numOperands; + unsigned NumOps = Desc->getNumOperands(); if (NumOps) { bool isTwoAddr = NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1; @@ -584,7 +584,7 @@ void Emitter::emitInstruction(const MachineInstr &MI, MCE.emitByte(0x0F); // If this is a two-address instruction, skip one of the register operands. - unsigned NumOps = Desc->numOperands; + unsigned NumOps = Desc->getNumOperands(); unsigned CurOp = 0; if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1) CurOp++; diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index 8c5d569e382..3d0d4238d23 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -597,7 +597,7 @@ void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { /// void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { MachineInstr *MI = I; - unsigned NumOps = MI->getDesc()->numOperands; + unsigned NumOps = MI->getDesc()->getNumOperands(); assert((NumOps == 5 || NumOps == 1) && "Can only handle fst* & ftst instructions!"); @@ -657,7 +657,7 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { /// void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { MachineInstr *MI = I; - unsigned NumOps = MI->getDesc()->numOperands; + unsigned NumOps = MI->getDesc()->getNumOperands(); assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!"); // Is this the last use of the source register? @@ -766,7 +766,7 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); MachineInstr *MI = I; - unsigned NumOperands = MI->getDesc()->numOperands; + unsigned NumOperands = MI->getDesc()->getNumOperands(); assert(NumOperands == 3 && "Illegal TwoArgFP instruction!"); unsigned Dest = getFPReg(MI->getOperand(0)); unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); @@ -864,7 +864,7 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); MachineInstr *MI = I; - unsigned NumOperands = MI->getDesc()->numOperands; + unsigned NumOperands = MI->getDesc()->getNumOperands(); assert(NumOperands == 2 && "Illegal FUCOM* instruction!"); unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index eb455ca8da6..cae382d64a3 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -1640,7 +1640,7 @@ static MachineInstr *FuseTwoAddrInst(unsigned Opcode, MIB.addImm(1).addReg(0).addImm(0); // Loop over the rest of the ri operands, converting them over. - unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2; + unsigned NumOps = MI->getDesc()->getNumOperands()-2; for (unsigned i = 0; i != NumOps; ++i) { MachineOperand &MO = MI->getOperand(i+2); MIB = X86InstrAddOperand(MIB, MO); @@ -1692,7 +1692,7 @@ X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i, SmallVector &MOs) const { const DenseMap *OpcodeTablePtr = NULL; bool isTwoAddrFold = false; - unsigned NumOps = getNumOperands(MI->getOpcode()); + unsigned NumOps = MI->getDesc()->getNumOperands(); bool isTwoAddr = NumOps > 1 && MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1; @@ -1798,7 +1798,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI, return NULL; SmallVector MOs; - unsigned NumOps = getNumOperands(LoadMI->getOpcode()); + unsigned NumOps = LoadMI->getDesc()->getNumOperands(); for (unsigned i = NumOps - 4; i != NumOps; ++i) MOs.push_back(LoadMI->getOperand(i)); return foldMemoryOperand(MI, Ops[0], MOs); @@ -1826,9 +1826,9 @@ bool X86InstrInfo::canFoldMemoryOperand(MachineInstr *MI, unsigned OpNum = Ops[0]; unsigned Opc = MI->getOpcode(); - unsigned NumOps = getNumOperands(Opc); + unsigned NumOps = MI->getDesc()->getNumOperands(); bool isTwoAddr = NumOps > 1 && - getOperandConstraint(Opc, 1, TOI::TIED_TO) != -1; + MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1; // Folding a memory location into the two-address part of a two-address // instruction is different than folding it other places. It requires @@ -2011,7 +2011,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, // Emit the data processing instruction. std::vector VTs; const TargetRegisterClass *DstRC = 0; - if (TID.numDefs > 0) { + if (TID.getNumDefs() > 0) { const TargetOperandInfo &DstTOI = TID.OpInfo[0]; DstRC = DstTOI.isLookupPtrRegClass() ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass); @@ -2019,7 +2019,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, } for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { MVT::ValueType VT = N->getValueType(i); - if (VT != MVT::Other && i >= TID.numDefs) + if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) VTs.push_back(VT); } if (Load)