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instead of aborting on shifts of i1, just implicitly fold them.

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The dag combiner can produce a shift of i1 when folding icmp i1's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53030 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2008-07-02 17:01:57 +00:00
parent 9d3edca443
commit 349db1738d
1 changed files with 7 additions and 1 deletions
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8
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -2192,7 +2192,13 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
assert(VT == N1.getValueType() && assert(VT == N1.getValueType() &&
"Shift operators return type must be the same as their first arg"); "Shift operators return type must be the same as their first arg");
assert(VT.isInteger() && N2.getValueType().isInteger() && assert(VT.isInteger() && N2.getValueType().isInteger() &&
VT != MVT::i1 && "Shifts only work on integers"); "Shifts only work on integers");
// Always fold shifts of i1 values so the code generator doesn't need to
// handle them. Since we know the size of the shift has to be less than the
// size of the value, the shift/rotate count is guaranteed to be zero.
if (VT == MVT::i1)
return N1;
break; break;
case ISD::FP_ROUND_INREG: { case ISD::FP_ROUND_INREG: {
MVT EVT = cast<VTSDNode>(N2)->getVT(); MVT EVT = cast<VTSDNode>(N2)->getVT();