mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-20 09:30:43 +00:00
Move SSE and AVX shuffle, unpack and compare code to more appropriate places
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106702 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
e9c59711d3
commit
34a491bd8e
@ -444,43 +444,6 @@ multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
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RC:$src1, (mem_frag addr:$src2)))], d>;
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}
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/// sse12_unpack_interleave - SSE 1 & 2 unpack and interleave
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multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
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PatFrag mem_frag, RegisterClass RC,
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X86MemOperand x86memop, string asm,
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Domain d> {
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def rr : PI<opc, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src2),
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asm, [(set RC:$dst,
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(vt (OpNode RC:$src1, RC:$src2)))], d>;
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def rm : PI<opc, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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asm, [(set RC:$dst,
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(vt (OpNode RC:$src1,
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(mem_frag addr:$src2))))], d>;
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}
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multiclass sse12_cmp<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int,
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string asm, Domain d, Operand sse_imm_op> {
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def rri : PIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$cc), asm,
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[(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
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def rmi : PIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, f128mem:$src, sse_imm_op:$cc), asm,
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[(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
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}
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// FIXME: rename instructions to only use the class above
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multiclass sse12_cmp_alt<RegisterClass RC, string asm, Domain d,
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Operand sse_imm_op> {
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def rri_alt : PIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$src2), asm,
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[], d>;
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def rmi_alt : PIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, f128mem:$src, sse_imm_op:$src2), asm,
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[], d>;
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}
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//===----------------------------------------------------------------------===//
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// SSE1 Instructions
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//===----------------------------------------------------------------------===//
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@ -741,6 +704,27 @@ let Constraints = "$src1 = $dst" in {
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// SSE 1 & 2 - Compare Instructions
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//===----------------------------------------------------------------------===//
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multiclass sse12_cmp<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int,
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string asm, Domain d, Operand sse_imm_op> {
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def rri : PIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$cc), asm,
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[(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
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def rmi : PIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, f128mem:$src, sse_imm_op:$cc), asm,
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[(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
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}
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// FIXME: rename instructions to only use the class above
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multiclass sse12_cmp_alt<RegisterClass RC, string asm, Domain d,
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Operand sse_imm_op> {
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def rri_alt : PIi8<0xC2, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$src2), asm,
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[], d>;
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def rmi_alt : PIi8<0xC2, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, f128mem:$src, sse_imm_op:$src2), asm,
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[], d>;
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}
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// Comparison instructions
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let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
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def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
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@ -860,6 +844,170 @@ def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
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(load addr:$src2)))]>;
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} // Defs = [EFLAGS]
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let Constraints = "$src1 = $dst" in {
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defm CMPPS : sse12_cmp<VR128, f128mem, int_x86_sse_cmp_ps,
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"cmp${cc}ps\t{$src, $dst|$dst, $src}", SSEPackedSingle, SSECC>,
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TB;
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defm CMPPD : sse12_cmp<VR128, f128mem, int_x86_sse2_cmp_pd,
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"cmp${cc}pd\t{$src, $dst|$dst, $src}", SSEPackedDouble, SSECC>,
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TB, OpSize;
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}
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let isAsmParserOnly = 1 in {
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defm VCMPPS : sse12_cmp<VR128, f128mem, int_x86_sse_cmp_ps,
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"cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
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SSEPackedSingle, SSECC>, VEX_4V;
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defm VCMPPD : sse12_cmp<VR128, f128mem, int_x86_sse2_cmp_pd,
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"cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
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SSEPackedSingle, SSECC>, OpSize, VEX_4V;
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}
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let isAsmParserOnly = 1, Pattern = []<dag> in {
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// Accept explicit immediate argument form instead of comparison code.
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let Constraints = "$src1 = $dst" in {
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defm CMPPS : sse12_cmp_alt<VR128,
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"cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
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SSEPackedSingle, i8imm>, TB;
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defm CMPPD : sse12_cmp_alt<VR128,
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"cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
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SSEPackedDouble, i8imm>, TB, OpSize;
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}
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defm VCMPPS : sse12_cmp_alt<VR128,
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"cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src}",
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SSEPackedSingle, i8imm>, VEX_4V;
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defm VCMPPD : sse12_cmp_alt<VR128,
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"cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
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SSEPackedSingle, i8imm>, OpSize, VEX_4V;
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}
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def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
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(CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
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def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
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(CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
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def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
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(CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
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def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
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(CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Shuffle Instructions
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//===----------------------------------------------------------------------===//
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/// sse12_shuffle - sse 1 & 2 shuffle instructions
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multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
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ValueType vt, string asm, PatFrag mem_frag,
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Domain d, bit IsConvertibleToThreeAddress = 0> {
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def rmi : PIi8<0xC6, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, i8imm:$src3), asm,
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[(set VR128:$dst, (vt (shufp:$src3
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VR128:$src1, (mem_frag addr:$src2))))], d>;
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let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
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def rri : PIi8<0xC6, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3), asm,
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[(set VR128:$dst,
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(vt (shufp:$src3 VR128:$src1, VR128:$src2)))], d>;
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}
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let isAsmParserOnly = 1 in {
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defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
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"shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
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memopv4f32, SSEPackedSingle>, VEX_4V;
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defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
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"shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
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memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
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"shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
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TB;
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defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
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"shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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memopv2f64, SSEPackedDouble>, TB, OpSize;
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Unpack Instructions
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//===----------------------------------------------------------------------===//
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/// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
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multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
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PatFrag mem_frag, RegisterClass RC,
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X86MemOperand x86memop, string asm,
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Domain d> {
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def rr : PI<opc, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, RC:$src2),
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asm, [(set RC:$dst,
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(vt (OpNode RC:$src1, RC:$src2)))], d>;
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def rm : PI<opc, MRMSrcMem,
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(outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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asm, [(set RC:$dst,
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(vt (OpNode RC:$src1,
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(mem_frag addr:$src2))))], d>;
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}
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let AddedComplexity = 10 in {
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let isAsmParserOnly = 1 in {
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defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
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VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, VEX_4V;
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defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
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VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, OpSize, VEX_4V;
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defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
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VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, VEX_4V;
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defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
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VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, OpSize, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
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VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
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SSEPackedSingle>, TB;
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defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
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VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
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SSEPackedDouble>, TB, OpSize;
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defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
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VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
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SSEPackedSingle>, TB;
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defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
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VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
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SSEPackedDouble>, TB, OpSize;
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} // Constraints = "$src1 = $dst"
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} // AddedComplexity
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Extract Floating-Point Sign mask
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//===----------------------------------------------------------------------===//
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/// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
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multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
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Domain d> {
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def rr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
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!strconcat(asm, "\t{$src, $dst|$dst, $src}"),
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[(set GR32:$dst, (Int RC:$src))], d>;
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}
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// Mask creation
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defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
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SSEPackedSingle>, TB;
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defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
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SSEPackedDouble>, TB, OpSize;
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let isAsmParserOnly = 1 in {
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defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
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"movmskps", SSEPackedSingle>, VEX;
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defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
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"movmskpd", SSEPackedDouble>, OpSize,
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VEX;
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
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//===----------------------------------------------------------------------===//
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// Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
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// names that start with 'Fs'.
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@ -1348,135 +1496,6 @@ defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
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defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
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int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
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// Compare
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let Constraints = "$src1 = $dst" in {
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defm CMPPS : sse12_cmp<VR128, f128mem, int_x86_sse_cmp_ps,
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"cmp${cc}ps\t{$src, $dst|$dst, $src}", SSEPackedSingle, SSECC>,
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TB;
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defm CMPPD : sse12_cmp<VR128, f128mem, int_x86_sse2_cmp_pd,
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"cmp${cc}pd\t{$src, $dst|$dst, $src}", SSEPackedDouble, SSECC>,
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TB, OpSize;
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}
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let isAsmParserOnly = 1 in {
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defm VCMPPS : sse12_cmp<VR128, f128mem, int_x86_sse_cmp_ps,
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"cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
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SSEPackedSingle, SSECC>, VEX_4V;
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defm VCMPPD : sse12_cmp<VR128, f128mem, int_x86_sse2_cmp_pd,
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"cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
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SSEPackedSingle, SSECC>, OpSize, VEX_4V;
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}
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let isAsmParserOnly = 1, Pattern = []<dag> in {
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// Accept explicit immediate argument form instead of comparison code.
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let Constraints = "$src1 = $dst" in {
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defm CMPPS : sse12_cmp_alt<VR128,
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"cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
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SSEPackedSingle, i8imm>, TB;
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defm CMPPD : sse12_cmp_alt<VR128,
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"cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
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SSEPackedDouble, i8imm>, TB, OpSize;
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}
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defm VCMPPS : sse12_cmp_alt<VR128,
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"cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src}",
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SSEPackedSingle, i8imm>, VEX_4V;
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defm VCMPPD : sse12_cmp_alt<VR128,
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"cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
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SSEPackedSingle, i8imm>, OpSize, VEX_4V;
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}
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def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
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(CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
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def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
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(CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
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def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
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(CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
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def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
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(CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
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// Shuffle and unpack instructions
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multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
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ValueType vt, string asm, PatFrag mem_frag,
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Domain d, bit IsConvertibleToThreeAddress = 0> {
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def rmi : PIi8<0xC6, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2, i8imm:$src3), asm,
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[(set VR128:$dst, (vt (shufp:$src3
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VR128:$src1, (mem_frag addr:$src2))))], d>;
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let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
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def rri : PIi8<0xC6, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3), asm,
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[(set VR128:$dst,
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(vt (shufp:$src3 VR128:$src1, VR128:$src2)))], d>;
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}
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let Constraints = "$src1 = $dst" in {
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defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
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"shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
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TB;
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defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
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"shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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memopv2f64, SSEPackedDouble>, TB, OpSize;
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|
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let Constraints = "", isAsmParserOnly = 1 in {
|
||||
defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
|
||||
"shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
|
||||
memopv4f32, SSEPackedSingle>, VEX_4V;
|
||||
defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
|
||||
"shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
|
||||
memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
|
||||
}
|
||||
|
||||
let AddedComplexity = 10 in {
|
||||
let Constraints = "", isAsmParserOnly = 1 in {
|
||||
defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
|
||||
VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
SSEPackedSingle>, VEX_4V;
|
||||
defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
|
||||
VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
SSEPackedDouble>, OpSize, VEX_4V;
|
||||
defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
|
||||
VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
SSEPackedSingle>, VEX_4V;
|
||||
defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
|
||||
VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
||||
SSEPackedDouble>, OpSize, VEX_4V;
|
||||
}
|
||||
defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
|
||||
VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
|
||||
SSEPackedSingle>, TB;
|
||||
defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
|
||||
VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
|
||||
SSEPackedDouble>, TB, OpSize;
|
||||
defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
|
||||
VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
|
||||
SSEPackedSingle>, TB;
|
||||
defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
|
||||
VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
|
||||
SSEPackedDouble>, TB, OpSize;
|
||||
} // AddedComplexity
|
||||
} // Constraints = "$src1 = $dst"
|
||||
|
||||
multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
|
||||
Domain d> {
|
||||
def rr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
|
||||
!strconcat(asm, "\t{$src, $dst|$dst, $src}"),
|
||||
[(set GR32:$dst, (Int RC:$src))], d>;
|
||||
}
|
||||
|
||||
// Mask creation
|
||||
defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
|
||||
SSEPackedSingle>, TB;
|
||||
defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
|
||||
SSEPackedDouble>, TB, OpSize;
|
||||
|
||||
let isAsmParserOnly = 1 in {
|
||||
defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
|
||||
"movmskps", SSEPackedSingle>, VEX;
|
||||
defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
|
||||
"movmskpd", SSEPackedDouble>, OpSize,
|
||||
VEX;
|
||||
}
|
||||
|
||||
// Prefetch intrinsic.
|
||||
def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
|
||||
"prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user