6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 04:30:12 +00:00
Code Issues Projects Releases Wiki Activity

Add mips32 r1 to the list of supported targets for Mips fast-isel

Browse Source 
Summary:
Expand list of supported targets for Mips to include mips32 r1.
Previously it only include r2. More patches are coming where there is 
a difference but in the current patches as pushed upstream, r1 and r2
are equivalent.

Test Plan:
simplestorefp1.ll

add new build bots at mips to test this flavor at both -O0 and -O2

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D5306

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217821 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler 2014-09-15 20:30:25 +00:00
parent 52d7b9c0aa
commit 34ad085eec
7 changed files with 37 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/Mips/MipsFastISel.cpp
View File

@ -61,7 +61,8 @@ public:
MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
Context = &funcInfo.Fn->getContext();
TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
(Subtarget->hasMips32r2() && (Subtarget->isABI_O32())));
((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
(Subtarget->isABI_O32())));
}
bool fastSelectInstruction(const Instruction *I) override;

2
test/CodeGen/Mips/Fast-ISel/loadstore2.ll
View File

@ -6,6 +6,8 @@ target triple = "mips--linux-gnu"
@c1 = common global i8 0, align 1
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@s2 = common global i16 0, align 2
@s1 = common global i16 0, align 2

2
test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
View File

@ -1,5 +1,7 @@
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
@s = common global i8* null, align 4

2
test/CodeGen/Mips/Fast-ISel/nullvoid.ll
View File

@ -1,5 +1,7 @@
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
; RUN: < %s | FileCheck %s
; Function Attrs: nounwind
define void @foo() {

2
test/CodeGen/Mips/Fast-ISel/simplestore.ll
View File

@ -1,5 +1,7 @@
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@abcd = external global i32

34
test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
View File

@ -1,5 +1,11 @@
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s -check-prefix=mips32r2
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
; RUN: < %s | FileCheck %s -check-prefix=mips32
@f = common global float 0.000000e+00, align 4
@de = common global double 0.000000e+00, align 8
@ -23,15 +29,25 @@ entry:
define void @d1() #0 {
entry:
store double 1.234567e+00, double* @de, align 8
; CHECK: .ent d1
; CHECK: lui $[[REG1a:[0-9]+]], 16371
; CHECK: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
; CHECK: lui $[[REG1b:[0-9]+]], 21403
; CHECK: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
; CHECK: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
; CHECK: mthc1 $[[REG2a]], $f[[REG3]]
; CHECK: sdc1 $f[[REG3]], 0(${{[0-9]+}})
; CHECK: .end d1
; mip32r2: .ent d1
; mips32r2: lui $[[REG1a:[0-9]+]], 16371
; mips32r2: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
; mips32r2: lui $[[REG1b:[0-9]+]], 21403
; mips32r2: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
; mips32r2: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
; mips32r2: mthc1 $[[REG2a]], $f[[REG3]]
; mips32r2: sdc1 $f[[REG3]], 0(${{[0-9]+}})
; mips32r2: .end d1
; mips32: .ent d1
; mips32: lui $[[REG1a:[0-9]+]], 16371
; mips32: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
; mips32: lui $[[REG1b:[0-9]+]], 21403
; mips32: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
; mips32: mtc1 $[[REG2a]], $f{{[0-9]+}}
; mips32: sdc1 $f[[REG3]], 0(${{[0-9]+}})
; mips32: .end d1
ret void
}

2
test/CodeGen/Mips/Fast-ISel/simplestorei.ll
View File

@ -1,5 +1,7 @@
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
; RUN: < %s | FileCheck %s
@ijk = external global i32