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R600: Remove unused InstrInfo::getMovImmInstr() function

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193178 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-10-22 18:19:01 +00:00
parent b62e1033a4
commit 34adeaf8b9
5 changed files with 0 additions and 31 deletions
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2
lib/Target/R600/AMDGPUInstrInfo.h
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@ -139,8 +139,6 @@ public:
// Pure virtual funtions to be implemented by sub-classes. // Pure virtual funtions to be implemented by sub-classes.
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
virtual MachineInstr* getMovImmInstr(MachineFunction *MF, unsigned DstReg,
int64_t Imm) const = 0;
virtual unsigned getIEQOpcode() const = 0; virtual unsigned getIEQOpcode() const = 0;
virtual bool isMov(unsigned opcode) const = 0; virtual bool isMov(unsigned opcode) const = 0;

12
lib/Target/R600/R600InstrInfo.cpp
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@ -77,18 +77,6 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
} }
} }
MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
unsigned DstReg, int64_t Imm) const {
MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
MachineInstrBuilder MIB(*MF, MI);
MIB.addReg(DstReg, RegState::Define);
MIB.addReg(AMDGPU::ALU_LITERAL_X);
MIB.addImm(Imm);
MIB.addReg(0); // PREDICATE_BIT
return MI;
}
unsigned R600InstrInfo::getIEQOpcode() const { unsigned R600InstrInfo::getIEQOpcode() const {
return AMDGPU::SETE_INT; return AMDGPU::SETE_INT;
} }

3
lib/Target/R600/R600InstrInfo.h
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@ -136,9 +136,6 @@ namespace llvm {
/// instruction slots within an instruction group. /// instruction slots within an instruction group.
bool isVector(const MachineInstr &MI) const; bool isVector(const MachineInstr &MI) const;
virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
int64_t Imm) const;
virtual unsigned getIEQOpcode() const; virtual unsigned getIEQOpcode() const;
virtual bool isMov(unsigned Opcode) const; virtual bool isMov(unsigned Opcode) const;

11
lib/Target/R600/SIInstrInfo.cpp
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@ -197,17 +197,6 @@ MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
return MI; return MI;
} }
MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
int64_t Imm) const {
MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_B32_e32), DebugLoc());
MachineInstrBuilder MIB(*MF, MI);
MIB.addReg(DstReg, RegState::Define);
MIB.addImm(Imm);
return MI;
}
bool SIInstrInfo::isMov(unsigned Opcode) const { bool SIInstrInfo::isMov(unsigned Opcode) const {
switch(Opcode) { switch(Opcode) {
default: return false; default: return false;

3
lib/Target/R600/SIInstrInfo.h
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@ -40,9 +40,6 @@ public:
virtual MachineInstr *commuteInstruction(MachineInstr *MI, virtual MachineInstr *commuteInstruction(MachineInstr *MI,
bool NewMI=false) const; bool NewMI=false) const;
virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
int64_t Imm) const;
virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;} virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;}
virtual bool isMov(unsigned Opcode) const; virtual bool isMov(unsigned Opcode) const;