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Comment typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120504 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -156,7 +156,7 @@ void LiveIntervalUnion::verify(LiveVirtRegBitSet& VisitedVRegs) {
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//
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// This design assumes only a fast mechanism for intersecting a single live
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// virtual register segment with a set of LiveIntervalUnion segments. This may
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// be ok since most VIRTREGs have very few segments. If we had a data
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// be ok since most virtual registers have very few segments. If we had a data
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// structure that optimizd MxN intersection of segments, then we would bypass
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// the loop that advances within the LiveInterval.
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//
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