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Tighten operand checking on CPS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1390,6 +1390,7 @@ class CPS<dag iops, string asm_ops>
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let Inst{4-0} = mode;
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}
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let DecoderMethod = "DecodeCPSInstruction" in {
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let M = 1 in
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def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
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"$imod\t$iflags, $mode">;
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@ -1398,6 +1399,7 @@ let mode = 0, M = 0 in
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let imod = 0, iflags = 0, M = 1 in
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def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
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}
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// Preload signals the memory system of possible future data/instruction access.
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// These are for disassembly only.
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@ -83,6 +83,8 @@ static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
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const void *Decoder);
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static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
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@ -1139,6 +1141,9 @@ static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
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unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
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unsigned mode = fieldFromInstruction32(Insn, 0, 5);
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// imod == '01' --> UNPREDICTABLE
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if (imod == 1) return false;
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if (M && mode && imod && iflags) {
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Inst.setOpcode(ARM::CPS3p);
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Inst.addOperand(MCOperand::CreateImm(imod));
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@ -1,5 +1,4 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
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# XFAIL: *
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# invalid imod value (0b01)
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0xc0 0x67 0x4 0xf1
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@ -1,5 +1,4 @@
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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
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# XFAIL: *
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# invalid (imod, M, iflags) combination
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0x93 0x1c 0x02 0xf1
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