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Add instruction encodings / disassembly support for rus instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2012-12-17 13:50:04 +00:00
parent 7f7d201d73
commit 35150cbf41
4 changed files with 124 additions and 19 deletions
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66
lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
View File

@ -72,6 +72,9 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus Decode2RInstruction(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
@ -87,6 +90,21 @@ static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
#include "XCoreGenDisassemblerTables.inc"
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
@ -101,6 +119,17 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (Val > 11)
return MCDisassembler::Fail;
static unsigned Values[] = {
32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
};
Inst.addOperand(MCOperand::CreateImm(Values[Val]));
return MCDisassembler::Success;
}
static DecodeStatus
Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
unsigned Combined = fieldFromInstruction(Insn, 6, 5) +
@ -152,6 +181,43 @@ Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
return S;
}
static DecodeStatus
DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
Inst.addOperand(MCOperand::CreateImm(Op2));
}
return S;
}
static DecodeStatus
DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeBitpOperand(Inst, Op2, Address, Decoder);
}
return S;
}
static DecodeStatus
DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;
DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeBitpOperand(Inst, Op2, Address, Decoder);
}
return S;
}
MCDisassembler::DecodeStatus
XCoreDisassembler::getInstruction(MCInst &instr,
uint64_t &Size,

20
lib/Target/XCore/XCoreInstrFormats.td
View File

@ -92,8 +92,26 @@ class _FR2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
let DecoderMethod = "DecodeR2RInstruction";
}
class _FRUS<dag outs, dag ins, string asmstr, list<dag> pattern>
class _FRUS<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> {
let Inst{15-11} = opc{5-1};
let Inst{4} = opc{0};
let DecoderMethod = "DecodeRUSInstruction";
}
// RUS with bitp operand
class _FRUSBitp<bits<6> opc, dag outs, dag ins, string asmstr,
list<dag> pattern>
: _FRUS<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "DecodeRUSBitpInstruction";
}
// RUS with first operand as both a source and a destination and a bitp second
// operand
class _FRUSSrcDstBitp<bits<6> opc, dag outs, dag ins, string asmstr,
list<dag> pattern>
: _FRUS<opc, outs, ins, asmstr, pattern> {
let DecoderMethod = "DecodeRUSSrcDstBitpInstruction";
}
class _FL2R<dag outs, dag ins, string asmstr, list<dag> pattern>

37
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -759,20 +759,22 @@ def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
"neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
let Constraints = "$src1 = $dst" in {
def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
"sext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
immBitp:$src2))]>;
def SEXT_rus :
_FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
"sext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
immBitp:$src2))]>;
def SEXT_2r :
_F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
"sext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
"zext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
immBitp:$src2))]>;
def ZEXT_rus :
_FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
"zext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
immBitp:$src2))]>;
def ZEXT_2r :
_F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
@ -786,17 +788,16 @@ def ANDNOT_2r :
}
let isReMaterializable = 1, neverHasSideEffects = 1 in
def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size),
"mkmsk $dst, $size",
[]>;
def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size),
"mkmsk $dst, $size", []>;
def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
"mkmsk $dst, $size",
[(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
def GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type),
"getr $dst, $type",
[(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type),
"getr $dst, $type",
[(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),
"getts $dst, res[$r]",
@ -810,7 +811,7 @@ def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
"outct res[$r], $val",
[(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
def OUTCT_rus : _F2RUS<(outs), (ins GRRegs:$r, i32imm:$val),
def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val),
"outct res[$r], $val",
[(int_xcore_outct GRRegs:$r, immUs:$val)]>;
@ -850,9 +851,9 @@ def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
"chkct res[$r], $val",
[(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
def CHKCT_rus : _F2RUS<(outs), (ins GRRegs:$r, i32imm:$val),
"chkct res[$r], $val",
[(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val),
"chkct res[$r], $val",
[(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),
"testct $dst, res[$src]",

20
test/MC/Disassembler/XCore/xcore.txt
View File

@ -138,3 +138,23 @@
# CHECK: sext r9, r1
0x45 0x37
# rus instructions
# CHECK: chkct res[r1], 8
0x34 0xcf
# CHECK: getr r11, 2
0x4e 0x87
# CHECK: mkmsk r4, 24
0x72 0xa7
# CHECK: outct res[r3], r0
0xcc 0x4e
# CHECK: sext r8, 16
0xb1 0x37
# CHECK: zext r2, 32
0xd8 0x46